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Statements

Subject Item
n2:RIV%2F00216305%3A26230%2F03%3APU42505%21RIV11-MSM-26230___
rdf:type
n16:Vysledek skos:Concept
dcterms:description
In the paper, the problem of feedback loops identification in a digital circuit is discussed. The alternative of a circuit representation as a mathematical structure - labelled directed graph - is presented. It is shown how mutual interconnections between circuit elements can be analysed - relation and adjacency matrices will be used for this purpose. It will be presented how to detect feedback loops in the circuit by means of mathematical operations on relation and adjacency matrices. The set of sequences of elements, each sequence represented by the list of elements in feedback loops is the output of the methodology. The principles of the methodology will be illustrated on an example. In the paper, the problem of feedback loops identification in a digital circuit is discussed. The alternative of a circuit representation as a mathematical structure - labelled directed graph - is presented. It is shown how mutual interconnections between circuit elements can be analysed - relation and adjacency matrices will be used for this purpose. It will be presented how to detect feedback loops in the circuit by means of mathematical operations on relation and adjacency matrices. The set of sequences of elements, each sequence represented by the list of elements in feedback loops is the output of the methodology. The principles of the methodology will be illustrated on an example.
dcterms:title
Proc. of IFAC Workshop on Programmable Devices and Systems Conference Proc. of IFAC Workshop on Programmable Devices and Systems Conference
skos:prefLabel
Proc. of IFAC Workshop on Programmable Devices and Systems Conference Proc. of IFAC Workshop on Programmable Devices and Systems Conference
skos:notation
RIV/00216305:26230/03:PU42505!RIV11-MSM-26230___
n3:aktivita
n9:N n9:P n9:V
n3:aktivity
N, P(GA102/01/1531), V
n3:dodaniDat
n11:2011
n3:domaciTvurceVysledku
n18:7825668 n18:9514740
n3:druhVysledku
n21:D
n3:duvernostUdaju
n13:S
n3:entitaPredkladatele
n5:predkladatel
n3:idSjednocenehoVysledku
623487
n3:idVysledku
RIV/00216305:26230/03:PU42505
n3:jazykVysledku
n6:eng
n3:klicovaSlova
adjacency matrix, register transfer level, testability analysis, data transporters, data processors, relations, graphs
n3:klicoveSlovo
n4:register%20transfer%20level n4:data%20processors n4:data%20transporters n4:relations n4:adjacency%20matrix n4:testability%20analysis n4:graphs
n3:kontrolniKodProRIV
[8AAACEE1BF7F]
n3:mistoKonaniAkce
Ostrava
n3:mistoVydani
Ostrava
n3:nazevZdroje
Proc. of IFAC Workshop on Programmable Devices and Systems Conference
n3:obor
n20:JC
n3:pocetDomacichTvurcuVysledku
2
n3:pocetTvurcuVysledku
2
n3:projekt
n15:GA102%2F01%2F1531
n3:rokUplatneniVysledku
n11:2003
n3:tvurceVysledku
Mika, Daniel Kotásek, Zdeněk
n3:typAkce
n7:WRD
n3:zahajeniAkce
2003-02-11+01:00
s:numberOfPages
6
n14:hasPublisher
Vysoká škola báňská - Technická univerzita Ostrava. Fakulta elektrotechniky a informatiky
n12:isbn
0-08-044130-0
n19:organizacniJednotka
26230