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Statements

Subject Item
n2:RIV%2F00216305%3A26230%2F01%3APU28732%21RIV11-MSM-26230___
rdf:type
skos:Concept n16:Vysledek
dcterms:description
The contribution shows a possibility to speed up image processing algorithms using a suitable combination of DSP and FPGA and also demonstrates methods to distribute the computational tasks between the DSP and FPGA. The contribution shows a possibility to speed up image processing algorithms using a suitable combination of DSP and FPGA and also demonstrates methods to distribute the computational tasks between the DSP and FPGA.
dcterms:title
Imaging Algorithm Speedup Using Co-Design Imaging Algorithm Speedup Using Co-Design
skos:prefLabel
Imaging Algorithm Speedup Using Co-Design Imaging Algorithm Speedup Using Co-Design
skos:notation
RIV/00216305:26230/01:PU28732!RIV11-MSM-26230___
n4:aktivita
n5:V n5:Z n5:N
n4:aktivity
N, V, Z(MSM 262200012)
n4:dodaniDat
n15:2011
n4:domaciTvurceVysledku
n7:3353443 n7:8736286 n7:9340386 n7:7313373
n4:druhVysledku
n19:D
n4:duvernostUdaju
n21:S
n4:entitaPredkladatele
n13:predkladatel
n4:idSjednocenehoVysledku
682380
n4:idVysledku
RIV/00216305:26230/01:PU28732
n4:jazykVysledku
n17:eng
n4:klicovaSlova
co-design, image processing, FPGA
n4:klicoveSlovo
n12:image%20processing n12:co-design n12:FPGA
n4:kontrolniKodProRIV
[7F06A7BEF402]
n4:mistoKonaniAkce
Štrbské Pleso
n4:mistoVydani
Štrbské Pleso
n4:nazevZdroje
Summaries Volume Process Control 01
n4:obor
n6:JC
n4:pocetDomacichTvurcuVysledku
4
n4:pocetTvurcuVysledku
4
n4:rokUplatneniVysledku
n15:2001
n4:tvurceVysledku
Zemčík, Pavel Richter, Miloslav Fučík, Otto Valenta, Pavel
n4:typAkce
n11:EUR
n4:zahajeniAkce
2001-06-11+02:00
n4:zamer
n8:MSM%20262200012
s:numberOfPages
2
n18:hasPublisher
Technická univerzita v Košiciach. Fakulta elektrotechniky a informatiky
n10:isbn
80-227-1542-5
n14:organizacniJednotka
26230