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Statements

Subject Item
n2:RIV%2F00216305%3A26220%2F12%3APU100472%21RIV13-MSM-26220___
rdf:type
skos:Concept n11:Vysledek
dcterms:description
This paper presents a study about the hardware implementation of the TCP/IP and UDP/IP headers compression for the point-to-point communication. The implementation is focused on the achievement of minimum latency and high compression ratio. The applied compression technique is a dictionary-based method. For the TCP/IP, the fixed length of the compressed header was implemented. On the contrary, the variable length of the compressed header was implemented for the UDP/IP. The dictionaries are filled from the original data on both sides. No additional transmissions are used for retaining the continuity of the dictionary content. This paper presents a study about the hardware implementation of the TCP/IP and UDP/IP headers compression for the point-to-point communication. The implementation is focused on the achievement of minimum latency and high compression ratio. The applied compression technique is a dictionary-based method. For the TCP/IP, the fixed length of the compressed header was implemented. On the contrary, the variable length of the compressed header was implemented for the UDP/IP. The dictionaries are filled from the original data on both sides. No additional transmissions are used for retaining the continuity of the dictionary content.
dcterms:title
1 Gbps Ethernet TCP/IP and UDP/IP Header Compression in FPGA 1 Gbps Ethernet TCP/IP and UDP/IP Header Compression in FPGA
skos:prefLabel
1 Gbps Ethernet TCP/IP and UDP/IP Header Compression in FPGA 1 Gbps Ethernet TCP/IP and UDP/IP Header Compression in FPGA
skos:notation
RIV/00216305:26220/12:PU100472!RIV13-MSM-26220___
n11:predkladatel
n12:orjk%3A26220
n3:aktivita
n16:S n16:P
n3:aktivity
P(ED2.1.00/03.0072), P(EE2.3.20.0007), P(LD11081), S
n3:dodaniDat
n21:2013
n3:domaciTvurceVysledku
Bobula, Marek n20:5940540 n20:4683994
n3:druhVysledku
n14:D
n3:duvernostUdaju
n19:S
n3:entitaPredkladatele
n8:predkladatel
n3:idSjednocenehoVysledku
183210
n3:idVysledku
RIV/00216305:26220/12:PU100472
n3:jazykVysledku
n15:eng
n3:klicovaSlova
Field Programable Gate Array (FPGA), Ethernet, header, compression, connection, IP, TCP, UDP
n3:klicoveSlovo
n7:Field%20Programable%20Gate%20Array%20%28FPGA%29 n7:header n7:compression n7:TCP n7:UDP n7:Ethernet n7:IP n7:connection
n3:kontrolniKodProRIV
[B63EE0B603DE]
n3:mistoKonaniAkce
Lisabon
n3:mistoVydani
Neuveden
n3:nazevZdroje
Proceedings of The Seventh International Conference on Systems and Networks Communications, ICSNC 2012
n3:obor
n5:JA
n3:pocetDomacichTvurcuVysledku
3
n3:pocetTvurcuVysledku
3
n3:projekt
n6:EE2.3.20.0007 n6:ED2.1.00%2F03.0072 n6:LD11081
n3:rokUplatneniVysledku
n21:2012
n3:tvurceVysledku
Fedra, Zbyněk Štohanzl, Milan Bobula, Marek
n3:typAkce
n17:WRD
n3:zahajeniAkce
2012-11-18+01:00
s:numberOfPages
7
n9:hasPublisher
Neuveden
n18:isbn
978-1-61208-231-8
n10:organizacniJednotka
26220