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Statements

Subject Item
n2:RIV%2F00216305%3A26220%2F11%3APU94781%21RIV13-MSM-26220___
rdf:type
skos:Concept n12:Vysledek
dcterms:description
In the paper, a synthesizable combinational integer number divider VHDL model is described that is suitable for implementation in the FPGA devices. The algorithm the divider is based on is briefly introduced. Along the model, testbench for its functional verification is presented. Results of implementation in Xilinx Spartan-3 and Spartan-6 devices - amount of FPGA resources used and maximum delay, are given in tables. In the paper, a synthesizable combinational integer number divider VHDL model is described that is suitable for implementation in the FPGA devices. The algorithm the divider is based on is briefly introduced. Along the model, testbench for its functional verification is presented. Results of implementation in Xilinx Spartan-3 and Spartan-6 devices - amount of FPGA resources used and maximum delay, are given in tables.
dcterms:title
VHDL Procedure for Combinational Divider VHDL Procedure for Combinational Divider
skos:prefLabel
VHDL Procedure for Combinational Divider VHDL Procedure for Combinational Divider
skos:notation
RIV/00216305:26220/11:PU94781!RIV13-MSM-26220___
n12:predkladatel
n13:orjk%3A26220
n3:aktivita
n14:Z n14:S n14:P
n3:aktivity
P(EE2.3.20.0007), P(GPP102/10/P513), S, Z(MSM0021630513)
n3:dodaniDat
n10:2013
n3:domaciTvurceVysledku
n18:8084556 n18:4683994
n3:druhVysledku
n21:D
n3:duvernostUdaju
n11:S
n3:entitaPredkladatele
n16:predkladatel
n3:idSjednocenehoVysledku
238326
n3:idVysledku
RIV/00216305:26220/11:PU94781
n3:jazykVysledku
n23:eng
n3:klicovaSlova
divider, FPGA, implementation, procedure, static timing analysis, VHDL
n3:klicoveSlovo
n15:implementation n15:procedure n15:FPGA n15:VHDL n15:static%20timing%20analysis n15:divider
n3:kontrolniKodProRIV
[EED537D3556B]
n3:mistoKonaniAkce
Budapest
n3:mistoVydani
Neuveden
n3:nazevZdroje
34th International Conference on Telecommunications and Signal Processing, TSP 2011
n3:obor
n17:JA
n3:pocetDomacichTvurcuVysledku
2
n3:pocetTvurcuVysledku
2
n3:projekt
n6:GPP102%2F10%2FP513 n6:EE2.3.20.0007
n3:rokUplatneniVysledku
n10:2011
n3:tvurceVysledku
Kolouch, Jaromír Fedra, Zbyněk
n3:typAkce
n4:WRD
n3:zahajeniAkce
2011-08-18+02:00
n3:zamer
n5:MSM0021630513
s:numberOfPages
3
n8:hasPublisher
Neuveden
n19:isbn
978-1-4577-1761-1
n20:organizacniJednotka
26220