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Statements

Subject Item
n2:RIV%2F00216305%3A26220%2F11%3APU94769%21RIV13-MSM-26220___
rdf:type
skos:Concept n8:Vysledek
dcterms:description
The paper presents a simple jitter measurement device implemented in FPGA. The device for the jitter measurement is closely coupled with a blind oversampling data recovery circuit (BO-CDR), which is sometimes used in asynchronous high speed data receivers as an alternative to the traditional PLL-based CDR circuit. The jitter measurement itself is based on estimating the edge density distribution over one unit interval via evaluating the number of detected edges in particular time intervals. The method enables simultaneous data transmission and real-time signal quality estimation without affecting the data signal, which is probably the main benefit of the proposed solution. There is no need for any additional hardware except the FPGA. The jitter evaluation is done completely within the gate array, requiring a few of its hardware resources. The proposed device was successfully implemented and tested on an optical data link. Real measurement results are presented together with reference measurements acqu The paper presents a simple jitter measurement device implemented in FPGA. The device for the jitter measurement is closely coupled with a blind oversampling data recovery circuit (BO-CDR), which is sometimes used in asynchronous high speed data receivers as an alternative to the traditional PLL-based CDR circuit. The jitter measurement itself is based on estimating the edge density distribution over one unit interval via evaluating the number of detected edges in particular time intervals. The method enables simultaneous data transmission and real-time signal quality estimation without affecting the data signal, which is probably the main benefit of the proposed solution. There is no need for any additional hardware except the FPGA. The jitter evaluation is done completely within the gate array, requiring a few of its hardware resources. The proposed device was successfully implemented and tested on an optical data link. Real measurement results are presented together with reference measurements acqu
dcterms:title
FPGA-based In-system Jitter Measurement FPGA-based In-system Jitter Measurement
skos:prefLabel
FPGA-based In-system Jitter Measurement FPGA-based In-system Jitter Measurement
skos:notation
RIV/00216305:26220/11:PU94769!RIV13-MSM-26220___
n8:predkladatel
n9:orjk%3A26220
n3:aktivita
n23:P n23:Z
n3:aktivity
P(ED2.1.00/03.0072), P(EE2.3.20.0007), P(GA102/09/0550), P(GAP102/11/1376), Z(MSM0021630513)
n3:dodaniDat
n18:2013
n3:domaciTvurceVysledku
n16:2878178 n16:1467379
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n19:D
n3:duvernostUdaju
n7:S
n3:entitaPredkladatele
n20:predkladatel
n3:idSjednocenehoVysledku
200268
n3:idVysledku
RIV/00216305:26220/11:PU94769
n3:jazykVysledku
n21:eng
n3:klicovaSlova
bit error rate, confidence level, FPGA, jitter
n3:klicoveSlovo
n4:confidence%20level n4:FPGA n4:jitter n4:bit%20error%20rate
n3:kontrolniKodProRIV
[6B8A9DC64112]
n3:mistoKonaniAkce
Praha
n3:mistoVydani
Technická 2, Praha 6, 166 27
n3:nazevZdroje
ISMOT Proceedings 2011
n3:obor
n22:JA
n3:pocetDomacichTvurcuVysledku
2
n3:pocetTvurcuVysledku
2
n3:projekt
n5:GAP102%2F11%2F1376 n5:GA102%2F09%2F0550 n5:ED2.1.00%2F03.0072 n5:EE2.3.20.0007
n3:rokUplatneniVysledku
n18:2011
n3:tvurceVysledku
Kubíček, Michal Kolka, Zdeněk
n3:typAkce
n13:EUR
n3:zahajeniAkce
2011-06-20+02:00
n3:zamer
n6:MSM0021630513
s:numberOfPages
4
n15:hasPublisher
Fakulta elektrotechniky, ČVUT
n17:isbn
978-80-01-04887-0
n12:organizacniJednotka
26220