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Statements

Subject Item
n2:RIV%2F00216305%3A26220%2F10%3APU86403%21RIV11-MSM-26220___
rdf:type
n12:Vysledek skos:Concept
dcterms:description
The paper is focused on the optimization and implementation of fully digital feed-forward blind oversampling CDR (BO-CDR). Two new phase-decision algorithms are proposed. Their complexity is very low, enabling a very simple and fast implementation even in FPGA, which was used as a development platform as well as a target device for the BO-CDR block. The FPGA-based optimization gave the opportunity to perform on-the-fly optimization under real conditions of target link. This greatly shortened the development time as there were no errors caused by inaccurate simulation models. Measurement results obtained on real links are included showing the jitter tolerance of the proposed algorithms to be comparable to the performance of modern PLL-based CDRs. The paper is focused on the optimization and implementation of fully digital feed-forward blind oversampling CDR (BO-CDR). Two new phase-decision algorithms are proposed. Their complexity is very low, enabling a very simple and fast implementation even in FPGA, which was used as a development platform as well as a target device for the BO-CDR block. The FPGA-based optimization gave the opportunity to perform on-the-fly optimization under real conditions of target link. This greatly shortened the development time as there were no errors caused by inaccurate simulation models. Measurement results obtained on real links are included showing the jitter tolerance of the proposed algorithms to be comparable to the performance of modern PLL-based CDRs.
dcterms:title
Blind Oversampling Data Recovery with Low Hardware Complexity Blind Oversampling Data Recovery with Low Hardware Complexity
skos:prefLabel
Blind Oversampling Data Recovery with Low Hardware Complexity Blind Oversampling Data Recovery with Low Hardware Complexity
skos:notation
RIV/00216305:26220/10:PU86403!RIV11-MSM-26220___
n6:aktivita
n18:R n18:S n18:P n18:Z
n6:aktivity
P(GA102/08/0851), P(GA102/09/0550), R, S, Z(MSM0021630513)
n6:cisloPeriodika
1
n6:dodaniDat
n10:2011
n6:domaciTvurceVysledku
n15:1467379 n15:2878178
n6:druhVysledku
n14:J
n6:duvernostUdaju
n7:S
n6:entitaPredkladatele
n19:predkladatel
n6:idSjednocenehoVysledku
249055
n6:idVysledku
RIV/00216305:26220/10:PU86403
n6:jazykVysledku
n11:eng
n6:klicovaSlova
Blind Oversampling CDR, FPGA, jitter.
n6:klicoveSlovo
n9:jitter. n9:Blind%20Oversampling%20CDR n9:FPGA
n6:kodStatuVydavatele
CZ - Česká republika
n6:kontrolniKodProRIV
[7751242E5DE6]
n6:nazevZdroje
Radioengineering
n6:obor
n13:JA
n6:pocetDomacichTvurcuVysledku
2
n6:pocetTvurcuVysledku
2
n6:projekt
n16:GA102%2F08%2F0851 n16:GA102%2F09%2F0550
n6:rokUplatneniVysledku
n10:2010
n6:svazekPeriodika
2010
n6:tvurceVysledku
Kolka, Zdeněk Kubíček, Michal
n6:zamer
n17:MSM0021630513
s:issn
1210-2512
s:numberOfPages
5
n5:organizacniJednotka
26220