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Statements

Subject Item
n2:RIV%2F00216305%3A26220%2F09%3APU81136%21RIV10-MSM-26220___
rdf:type
n7:Vysledek skos:Concept
dcterms:description
The paper describes multi-core computing unit implemented into FPGA chip. The unit is used for accelerating of Artificial Neural Networks computations. The paper describes multi-core computing unit implemented into FPGA chip. The unit is used for accelerating of Artificial Neural Networks computations.
dcterms:title
Multi-Core Computing Unit for Artificial Neural Networks in FPGA Chip Multi-Core Computing Unit for Artificial Neural Networks in FPGA Chip
skos:prefLabel
Multi-Core Computing Unit for Artificial Neural Networks in FPGA Chip Multi-Core Computing Unit for Artificial Neural Networks in FPGA Chip
skos:notation
RIV/00216305:26220/09:PU81136!RIV10-MSM-26220___
n4:aktivita
n13:P n13:Z
n4:aktivity
P(GA102/08/1116), Z(MSM0021630503)
n4:dodaniDat
n12:2010
n4:domaciTvurceVysledku
Bohrn, Marek n14:4135660 n14:3071138
n4:druhVysledku
n11:D
n4:duvernostUdaju
n17:S
n4:entitaPredkladatele
n19:predkladatel
n4:idSjednocenehoVysledku
327931
n4:idVysledku
RIV/00216305:26220/09:PU81136
n4:jazykVysledku
n10:eng
n4:klicovaSlova
Artificial neural networks, Computation acceleration, FPGA, VHDL, Spartan-3
n4:klicoveSlovo
n8:Artificial%20neural%20networks n8:Spartan-3 n8:Computation%20acceleration n8:VHDL n8:FPGA
n4:kontrolniKodProRIV
[6AF61E5BE3FD]
n4:mistoKonaniAkce
Milano
n4:mistoVydani
Portugal
n4:nazevZdroje
ICINCO 2009 6th International Conference on Informatics in Control, Automationa and Robotics Proceedings Volume 1 - Inteligent Control Systems and Optimization
n4:obor
n16:JA
n4:pocetDomacichTvurcuVysledku
3
n4:pocetTvurcuVysledku
3
n4:projekt
n20:GA102%2F08%2F1116
n4:rokUplatneniVysledku
n12:2009
n4:tvurceVysledku
Vrba, Radimír Bohrn, Marek Fujcik, Lukáš
n4:typAkce
n21:WRD
n4:zahajeniAkce
2009-07-02+02:00
n4:zamer
n5:MSM0021630503
s:numberOfPages
4
n22:hasPublisher
INSTICC PRESS
n9:isbn
978-989-8111-99-9
n18:organizacniJednotka
26220