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Statements

Subject Item
n2:RIV%2F00216305%3A26220%2F08%3APU73748%21RIV10-MSM-26220___
rdf:type
n18:Vysledek skos:Concept
dcterms:description
This paper is focused on design aspects of a fractional-N PLL (Phase Locked Loop) based frequency synthesizer proposed for the Mobile WiMAX (Worldwide Interoperability for Mobile Access) standard. Requirements in terms of phase noise, settling time, frequency resolution and frequency of operation for WiMAX frequency synthesizer are presented. Furthermore, a high-speed CP (Charge Pump) PLL based synthesizer with a switched loop bandwidth is proposed and simulated. It has a 32 MHz reference frequency and a 50 kHz loop bandwidth with frequency raster of 125 kHz and 14 us settling time. This paper is focused on design aspects of a fractional-N PLL (Phase Locked Loop) based frequency synthesizer proposed for the Mobile WiMAX (Worldwide Interoperability for Mobile Access) standard. Requirements in terms of phase noise, settling time, frequency resolution and frequency of operation for WiMAX frequency synthesizer are presented. Furthermore, a high-speed CP (Charge Pump) PLL based synthesizer with a switched loop bandwidth is proposed and simulated. It has a 32 MHz reference frequency and a 50 kHz loop bandwidth with frequency raster of 125 kHz and 14 us settling time.
dcterms:title
Analysis of a PLL Based Frequency Synthesizer using Switched Loop Bandwidth for Mobile WiMAX Analysis of a PLL Based Frequency Synthesizer using Switched Loop Bandwidth for Mobile WiMAX
skos:prefLabel
Analysis of a PLL Based Frequency Synthesizer using Switched Loop Bandwidth for Mobile WiMAX Analysis of a PLL Based Frequency Synthesizer using Switched Loop Bandwidth for Mobile WiMAX
skos:notation
RIV/00216305:26220/08:PU73748!RIV10-MSM-26220___
n3:aktivita
n15:Z n15:P
n3:aktivity
P(GD102/08/H027), Z(MSM0021630513)
n3:dodaniDat
n8:2010
n3:domaciTvurceVysledku
n17:8304262
n3:druhVysledku
n4:D
n3:duvernostUdaju
n14:S
n3:entitaPredkladatele
n22:predkladatel
n3:idSjednocenehoVysledku
355763
n3:idVysledku
RIV/00216305:26220/08:PU73748
n3:jazykVysledku
n5:eng
n3:klicovaSlova
Fractional-N frequency synthesizers, high-speed electronics, phase locked loops, phase noise.
n3:klicoveSlovo
n6:phase%20locked%20loops n6:phase%20noise. n6:Fractional-N%20frequency%20synthesizers n6:high-speed%20electronics
n3:kontrolniKodProRIV
[AD6B1AB0F290]
n3:mistoKonaniAkce
Praha
n3:mistoVydani
Praha
n3:nazevZdroje
Proceedings of the 18th International Conference Radioelektronika 2008
n3:obor
n21:JA
n3:pocetDomacichTvurcuVysledku
1
n3:pocetTvurcuVysledku
3
n3:projekt
n9:GD102%2F08%2FH027
n3:rokUplatneniVysledku
n8:2008
n3:tvurceVysledku
Baudoin, Genevieve Valenta, Václav Villegas, Martine
n3:typAkce
n11:EUR
n3:zahajeniAkce
2008-04-23+02:00
n3:zamer
n19:MSM0021630513
s:numberOfPages
4
n10:hasPublisher
Czechoslovakia Section IEEE
n20:isbn
978-1-4244-2087-2
n16:organizacniJednotka
26220