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Namespace Prefixes

PrefixIRI
n7http://linked.opendata.cz/ontology/domain/vavai/riv/typAkce/
dctermshttp://purl.org/dc/terms/
n22http://localhost/temp/predkladatel/
n14http://purl.org/net/nknouf/ns/bibtex#
n19http://linked.opendata.cz/resource/domain/vavai/projekt/
n16http://linked.opendata.cz/resource/domain/vavai/riv/tvurce/
n6http://linked.opendata.cz/ontology/domain/vavai/
n12https://schema.org/
n11http://linked.opendata.cz/resource/domain/vavai/zamer/
shttp://schema.org/
n4http://linked.opendata.cz/ontology/domain/vavai/riv/
skoshttp://www.w3.org/2004/02/skos/core#
n13http://linked.opendata.cz/resource/domain/vavai/vysledek/RIV%2F00216305%3A26220%2F06%3APU63772%21RIV07-GA0-26220___/
n2http://linked.opendata.cz/resource/domain/vavai/vysledek/
rdfhttp://www.w3.org/1999/02/22-rdf-syntax-ns#
n21http://linked.opendata.cz/ontology/domain/vavai/riv/klicoveSlovo/
n20http://linked.opendata.cz/ontology/domain/vavai/riv/duvernostUdaju/
xsdhhttp://www.w3.org/2001/XMLSchema#
n8http://linked.opendata.cz/ontology/domain/vavai/riv/jazykVysledku/
n5http://linked.opendata.cz/ontology/domain/vavai/riv/aktivita/
n18http://linked.opendata.cz/ontology/domain/vavai/riv/obor/
n9http://linked.opendata.cz/ontology/domain/vavai/riv/druhVysledku/
n17http://reference.data.gov.uk/id/gregorian-year/

Statements

Subject Item
n2:RIV%2F00216305%3A26220%2F06%3APU63772%21RIV07-GA0-26220___
rdf:type
n6:Vysledek skos:Concept
dcterms:description
This paper describes steps involved in a VHDL design of digital decimation filter for multibit sigma-delta (ΣΔ) modulator. Parameters of decimation filter are derived from the specification of the multibit Σ∆ modulator with two-step quantization architecture. Using Matlabtool it is possible to find the filter order, the required quantizationlevel for the coefficients and their values. Finally, by analyzing the design, we can find an efficient way to implement the filter in hardware. This structure is designed in two versions using VHDL. The design is programmed and tested on a Xilinx FPGA –Spartan 3 XC3S200-5FT256. Článek popisuje kroky při návrhu decimačního filtru v jazyce VHDL pro vícebitový sigma-delta modulátor. Parametry decimačního filtru jsou odvozeny ze specifikace vícebitového sigma-delta modulátoru se dvěma kroky kvantovacího procesu. Návrh decimačního filtru byl proveden teoreticky v programu Matlab. Výsledná implementace byla provedena v obvodu Xilinx FPGA Spartan 3 XC3S200-5FT256. This paper describes steps involved in a VHDL design of digital decimation filter for multibit sigma-delta (ΣΔ) modulator. Parameters of decimation filter are derived from the specification of the multibit Σ∆ modulator with two-step quantization architecture. Using Matlabtool it is possible to find the filter order, the required quantizationlevel for the coefficients and their values. Finally, by analyzing the design, we can find an efficient way to implement the filter in hardware. This structure is designed in two versions using VHDL. The design is programmed and tested on a Xilinx FPGA –Spartan 3 XC3S200-5FT256.
dcterms:title
DESIGN OF DECIMATION FILTER FOR MULTIBIT SIGMA-DELTA MODULATOR WITH TWO-STEP QUANTIZATION Návrh decimačního filtru pro vícebitový sigma-delta modulátor se dvěma kroky kvantovacího procesu. DESIGN OF DECIMATION FILTER FOR MULTIBIT SIGMA-DELTA MODULATOR WITH TWO-STEP QUANTIZATION
skos:prefLabel
DESIGN OF DECIMATION FILTER FOR MULTIBIT SIGMA-DELTA MODULATOR WITH TWO-STEP QUANTIZATION Návrh decimačního filtru pro vícebitový sigma-delta modulátor se dvěma kroky kvantovacího procesu. DESIGN OF DECIMATION FILTER FOR MULTIBIT SIGMA-DELTA MODULATOR WITH TWO-STEP QUANTIZATION
skos:notation
RIV/00216305:26220/06:PU63772!RIV07-GA0-26220___
n4:strany
83-86
n4:aktivita
n5:P n5:Z
n4:aktivity
P(GA102/05/0869), Z(MSM0021630503)
n4:dodaniDat
n17:2007
n4:domaciTvurceVysledku
n16:3071138 Mougel, Thibault
n4:druhVysledku
n9:D
n4:duvernostUdaju
n20:S
n4:entitaPredkladatele
n13:predkladatel
n4:idSjednocenehoVysledku
470940
n4:idVysledku
RIV/00216305:26220/06:PU63772
n4:jazykVysledku
n8:eng
n4:klicovaSlova
decimation filter, programmable logic device
n4:klicoveSlovo
n21:decimation%20filter n21:programmable%20logic%20device
n4:kontrolniKodProRIV
[584EECD2EF49]
n4:mistoKonaniAkce
Gdynia
n4:mistoVydani
Gdynia
n4:nazevZdroje
Proceedings of the International Conference, Mixed Design of Integrated Circuits and Systems
n4:obor
n18:JA
n4:pocetDomacichTvurcuVysledku
2
n4:pocetTvurcuVysledku
2
n4:projekt
n19:GA102%2F05%2F0869
n4:rokUplatneniVysledku
n17:2006
n4:tvurceVysledku
Mougel, Thibault Fujcik, Lukáš
n4:typAkce
n7:CST
n4:zahajeniAkce
2006-06-22+02:00
n4:zamer
n11:MSM0021630503
s:numberOfPages
4
n14:hasPublisher
Neuveden
n12:isbn
83-922632-1-9
n22:organizacniJednotka
26220