This HTML5 document contains 48 embedded RDF statements represented using HTML+Microdata notation.

The embedded RDF content will be recognized by any processor of HTML5 Microdata.

Namespace Prefixes

PrefixIRI
n10http://linked.opendata.cz/ontology/domain/vavai/riv/typAkce/
dctermshttp://purl.org/dc/terms/
n22http://localhost/temp/predkladatel/
n6http://purl.org/net/nknouf/ns/bibtex#
n14http://linked.opendata.cz/resource/domain/vavai/riv/tvurce/
n8http://linked.opendata.cz/resource/domain/vavai/projekt/
n12http://linked.opendata.cz/ontology/domain/vavai/
n15https://schema.org/
n13http://linked.opendata.cz/resource/domain/vavai/zamer/
shttp://schema.org/
n4http://linked.opendata.cz/ontology/domain/vavai/riv/
skoshttp://www.w3.org/2004/02/skos/core#
n2http://linked.opendata.cz/resource/domain/vavai/vysledek/
rdfhttp://www.w3.org/1999/02/22-rdf-syntax-ns#
n16http://linked.opendata.cz/resource/domain/vavai/vysledek/RIV%2F00216305%3A26220%2F06%3APU57572%21RIV10-MSM-26220___/
n7http://linked.opendata.cz/ontology/domain/vavai/riv/klicoveSlovo/
n9http://linked.opendata.cz/ontology/domain/vavai/riv/duvernostUdaju/
xsdhhttp://www.w3.org/2001/XMLSchema#
n21http://linked.opendata.cz/ontology/domain/vavai/riv/aktivita/
n19http://linked.opendata.cz/ontology/domain/vavai/riv/jazykVysledku/
n20http://linked.opendata.cz/ontology/domain/vavai/riv/obor/
n18http://linked.opendata.cz/ontology/domain/vavai/riv/druhVysledku/
n11http://reference.data.gov.uk/id/gregorian-year/

Statements

Subject Item
n2:RIV%2F00216305%3A26220%2F06%3APU57572%21RIV10-MSM-26220___
rdf:type
skos:Concept n12:Vysledek
dcterms:description
This paper presents a novel architecture of high-order single-stage sigma-delta (ΣΔ) converter for sensor measurement. The two-step quantization technique was utilized to design of novel architecture of ΣΔ modulator. The time steps are interleaved to achieve resolution improvement without decreasing of conversion speed. This technique can be useful for low oversampling ratio. The novel architecture was designed to obtain high dynamic range of input signal, high signal-to-noise ratio and high reliability. This paper describes steps involved in a new VHDL design of a decimation filter for a ΣΔ modulator. Parameters of decimation filter are derived from the specifications of the overall ΣΔ modulator. The proposed architecture of switched-capacitor (SC) ΣΔ modulator was simulated with nonidealities blocks, such as sampling jitter, noise, and operational amplifier parameters (white noise, finite dc gain, finite bandwidth, slew rate and saturation voltages) This paper presents a novel architecture of high-order single-stage sigma-delta (ΣΔ) converter for sensor measurement. The two-step quantization technique was utilized to design of novel architecture of ΣΔ modulator. The time steps are interleaved to achieve resolution improvement without decreasing of conversion speed. This technique can be useful for low oversampling ratio. The novel architecture was designed to obtain high dynamic range of input signal, high signal-to-noise ratio and high reliability. This paper describes steps involved in a new VHDL design of a decimation filter for a ΣΔ modulator. Parameters of decimation filter are derived from the specifications of the overall ΣΔ modulator. The proposed architecture of switched-capacitor (SC) ΣΔ modulator was simulated with nonidealities blocks, such as sampling jitter, noise, and operational amplifier parameters (white noise, finite dc gain, finite bandwidth, slew rate and saturation voltages)
dcterms:title
Modeling and design of novel architecture of multibit switched-capacitor sigma-delta converter with two-step quantization process Modeling and design of novel architecture of multibit switched-capacitor sigma-delta converter with two-step quantization process
skos:prefLabel
Modeling and design of novel architecture of multibit switched-capacitor sigma-delta converter with two-step quantization process Modeling and design of novel architecture of multibit switched-capacitor sigma-delta converter with two-step quantization process
skos:notation
RIV/00216305:26220/06:PU57572!RIV10-MSM-26220___
n4:aktivita
n21:P n21:Z
n4:aktivity
P(GA102/05/0869), P(GD102/03/H105), Z(MSM0021630503)
n4:dodaniDat
n11:2010
n4:domaciTvurceVysledku
n14:1904345 Mougel, Thibault n14:3071138 n14:4135660
n4:druhVysledku
n18:D
n4:duvernostUdaju
n9:S
n4:entitaPredkladatele
n16:predkladatel
n4:idSjednocenehoVysledku
486144
n4:idVysledku
RIV/00216305:26220/06:PU57572
n4:jazykVysledku
n19:eng
n4:klicovaSlova
sigma-delta modulation, decimation filter, analog-to -digital conversion
n4:klicoveSlovo
n7:sigma-delta%20modulation n7:decimation%20filter n7:analog-to%20-digital%20conversion
n4:kontrolniKodProRIV
[AF3104BFA13C]
n4:mistoKonaniAkce
Morne
n4:mistoVydani
NEUVEDEN
n4:nazevZdroje
The International Conference on Systems, IEEE Computer Society
n4:obor
n20:JA
n4:pocetDomacichTvurcuVysledku
4
n4:pocetTvurcuVysledku
4
n4:projekt
n8:GD102%2F03%2FH105 n8:GA102%2F05%2F0869
n4:rokUplatneniVysledku
n11:2006
n4:tvurceVysledku
Háze, Jiří Mougel, Thibault Vrba, Radimír Fujcik, Lukáš
n4:typAkce
n10:WRD
n4:zahajeniAkce
2006-04-26+02:00
n4:zamer
n13:MSM0021630503
s:numberOfPages
6
n6:hasPublisher
Morne, Mauritius
n15:isbn
0-7695-2540-7
n22:organizacniJednotka
26220