About: Quadrature Linear Digital Modulator Implementation in VHDL

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An Entity of Type : http://linked.opendata.cz/ontology/domain/vavai/Vysledek, within Data Space : linked.opendata.cz associated with source document(s)

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rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	In this article we describe our effort to create, model, implement and simulate a quadrature linear digital modulator. It is to be used as a part of advanced radio transmission system. We describe the process of modeling the modulator in Matlab in both floating and fixed point arithmetic for later implementation in VHDL language for FPGA. We also describe the techniques we have used to implement the modulator in digital domain using efficient parallel structure with elimination of multiplication operation. The complete system is then being simulated in ModelSim, compared with the model and results are presented and evaluated. In this article we describe our effort to create, model, implement and simulate a quadrature linear digital modulator. It is to be used as a part of advanced radio transmission system. We describe the process of modeling the modulator in Matlab in both floating and fixed point arithmetic for later implementation in VHDL language for FPGA. We also describe the techniques we have used to implement the modulator in digital domain using efficient parallel structure with elimination of multiplication operation. The complete system is then being simulated in ModelSim, compared with the model and results are presented and evaluated. (en)
Title	Quadrature Linear Digital Modulator Implementation in VHDL Quadrature Linear Digital Modulator Implementation in VHDL (en)
skos:prefLabel	Quadrature Linear Digital Modulator Implementation in VHDL Quadrature Linear Digital Modulator Implementation in VHDL (en)
skos:notation	RIV/68407700:21230/10:00170715!RIV11-GA0-21230___
http://linked.open...avai/riv/aktivita	P S Z
http://linked.open...avai/riv/aktivity	P(FI-IM5/115), P(GAP102/10/1320), S, Z(MSM6840770014)
http://linked.open...vai/riv/dodaniDat	2011
http://linked.open...aciTvurceVysledku	Klíma, Miloš Boháč, Leoš Kekrt, Daniel Podgorný, Radek
http://linked.open.../riv/druhVysledku	D - Článek ve sborníku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	České vysoké učení technické v Praze / Fakulta elektrotechnická
http://linked.open...dnocenehoVysledku	283568
http://linked.open...ai/riv/idVysledku	RIV/68407700:21230/10:00170715
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	VHDL; simulation; modeling; implementation; digital modulations (en)
http://linked.open.../riv/klicoveSlovo	VHDL implementation modeling simulation digital modulations
http://linked.open...ontrolniKodProRIV	[CEDB6871CA12]
http://linked.open...v/mistoKonaniAkce	Plzeň
http://linked.open...i/riv/mistoVydani	Pilsen
http://linked.open...i/riv/nazevZdroje	Applied Electronic 2010
http://linked.open...in/vavai/riv/obor	JA
http://linked.open...ichTvurcuVysledku	4 (xsd:int)
http://linked.open...cetTvurcuVysledku	4 (xsd:int)
http://linked.open...vavai/riv/projekt	Research and modeling of advanced methods of image quality evaluation *Adaptive High-rate Point-to-point Microwave Line Featured by the Transmission Rate of 256 Mbit/s and Adaptive Power Control System
http://linked.open...UplatneniVysledku	2010
http://linked.open...iv/tvurceVysledku	Boháč, Leoš Klíma, Miloš Kekrt, Daniel Podgorný, Radek
http://linked.open...vavai/riv/typAkce	EUR - Evropská
http://linked.open.../riv/zahajeniAkce	2010-09-08 (xsd:date)
http://linked.open...n/vavai/riv/zamer	Výzkum perspektivních informačních a komunikačních technologií
issn	1803-7232
number of pages	6 (xsd:int)
http://purl.org/ne...btex#hasPublisher	Západočeská univerzita v Plzni
https://schema.org/isbn	978-80-7043-865-7
http://localhost/t...ganizacniJednotka	21230
is http://linked.open...avai/riv/vysledek of	Quadrature Linear Digital Modulator Implementation in VHDL

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