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  • This software implements Speeded Up Robust Features (SURF) on a Field Programmable Gate Array (FPGA). The SURF algorithm extracts salient points from image and computes descriptors of their surroundings that are invariant to scale, rotation and illumination changes. The interest point detection and feature descriptor extraction algorithm is often used as the first stage in autonomous robot navigation, object recognition and tracking etc. However, detection and extraction are computationally demanding and therefore can't be used in systems with limited computational power. We took advantage of algorithm's natural parallelism and implemented it's most demanding parts in FPGA logic. Several modifications of the original algorithm have been made to increase it's suitability for FPGA implementation. Experiments show, that the FPGA implementation is comparable in terms of precision, speed and repeatability, but outperforms the CPU and GPU implementation in terms of power consumption.
  • This software implements Speeded Up Robust Features (SURF) on a Field Programmable Gate Array (FPGA). The SURF algorithm extracts salient points from image and computes descriptors of their surroundings that are invariant to scale, rotation and illumination changes. The interest point detection and feature descriptor extraction algorithm is often used as the first stage in autonomous robot navigation, object recognition and tracking etc. However, detection and extraction are computationally demanding and therefore can't be used in systems with limited computational power. We took advantage of algorithm's natural parallelism and implemented it's most demanding parts in FPGA logic. Several modifications of the original algorithm have been made to increase it's suitability for FPGA implementation. Experiments show, that the FPGA implementation is comparable in terms of precision, speed and repeatability, but outperforms the CPU and GPU implementation in terms of power consumption. (en)
Title
  • FPGA-based Speeded Up Robust Features
  • FPGA-based Speeded Up Robust Features (en)
skos:prefLabel
  • FPGA-based Speeded Up Robust Features
  • FPGA-based Speeded Up Robust Features (en)
skos:notation
  • RIV/68407700:21230/10:00167810!RIV11-MSM-21230___
http://linked.open...avai/riv/aktivita
http://linked.open...avai/riv/aktivity
  • P(2C06005), R, V, Z(MSM6840770038)
http://linked.open...vai/riv/dodaniDat
http://linked.open...aciTvurceVysledku
http://linked.open.../riv/druhVysledku
http://linked.open...iv/duvernostUdaju
http://linked.open...onomickeParametry
  • nejsou stanoveny
http://linked.open...titaPredkladatele
http://linked.open...dnocenehoVysledku
  • 259679
http://linked.open...ai/riv/idVysledku
  • RIV/68407700:21230/10:00167810
http://linked.open...terniIdentifikace
  • FPGA-SURF
http://linked.open...riv/jazykVysledku
http://linked.open.../riv/klicovaSlova
  • image processing; SURF; FPGA (en)
http://linked.open.../riv/klicoveSlovo
http://linked.open...ontrolniKodProRIV
  • [ACF0DCEA92ED]
http://linked.open.../licencniPoplatek
http://linked.open...okalizaceVysledku
http://linked.open...in/vavai/riv/obor
http://linked.open...ichTvurcuVysledku
http://linked.open...cetTvurcuVysledku
http://linked.open...vavai/riv/projekt
http://linked.open...UplatneniVysledku
http://linked.open...echnickeParametry
  • Binární kód jazyka HDL %22netlist%22
http://linked.open...iv/tvurceVysledku
  • Faigl, Jan
  • Krajník, Tomáš
  • Přeučil, Libor
  • Šváb, J.
http://linked.open...avai/riv/vlastnik
http://linked.open...itiJinymSubjektem
http://linked.open...n/vavai/riv/zamer
http://localhost/t...ganizacniJednotka
  • 21230
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