About: FPGA-based Speeded Up Robust Features

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An Entity of Type : http://linked.opendata.cz/ontology/domain/vavai/Vysledek, within Data Space : linked.opendata.cz associated with source document(s)

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rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	We present an implementation of the Speeded Up Robust Features (SURF) on a Field Programmable Gate Array (FPGA). The SURF algorithm extracts salient points from image and computes descriptors of their surroundings that are invariant to scale, rotation and illumination changes. The interest point detection and feature descriptor extraction algorithm is often used as the first stage in autonomous robot navigation, object recognition and tracking etc. However, detection and extraction are computationally demanding and therefore can't be used in systems with limited computational power. We took advantage of algorithm's natural parallelism and implemented it's most demanding parts in FPGA logic. Several modifications of the original algorithm have been made to increase it's suitability for FPGA implementation. We present an implementation of the Speeded Up Robust Features (SURF) on a Field Programmable Gate Array (FPGA). The SURF algorithm extracts salient points from image and computes descriptors of their surroundings that are invariant to scale, rotation and illumination changes. The interest point detection and feature descriptor extraction algorithm is often used as the first stage in autonomous robot navigation, object recognition and tracking etc. However, detection and extraction are computationally demanding and therefore can't be used in systems with limited computational power. We took advantage of algorithm's natural parallelism and implemented it's most demanding parts in FPGA logic. Several modifications of the original algorithm have been made to increase it's suitability for FPGA implementation. (en)
Title	FPGA-based Speeded Up Robust Features FPGA-based Speeded Up Robust Features (en)
skos:prefLabel	FPGA-based Speeded Up Robust Features FPGA-based Speeded Up Robust Features (en)
skos:notation	RIV/68407700:21230/09:00159088!RIV13-MSM-21230___
http://linked.open...avai/riv/aktivita	P Z
http://linked.open...avai/riv/aktivity	P(2C06005), P(7E08006), Z(MSM6840770038)
http://linked.open...vai/riv/dodaniDat	2013
http://linked.open...aciTvurceVysledku	Šváb, Jan Přeučil, Libor Krajník, Tomáš Faigl, Jan
http://linked.open.../riv/druhVysledku	D - Článek ve sborníku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	České vysoké učení technické v Praze / Fakulta elektrotechnická
http://linked.open...dnocenehoVysledku	315483
http://linked.open...ai/riv/idVysledku	RIV/68407700:21230/09:00159088
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	machine vision; visual navigation; SURF; FPGA (en)
http://linked.open.../riv/klicoveSlovo	SURF machine vision FPGA visual navigation
http://linked.open...ontrolniKodProRIV	[1F0744F51FA2]
http://linked.open...v/mistoKonaniAkce	Woburn
http://linked.open...i/riv/mistoVydani	Boston
http://linked.open...i/riv/nazevZdroje	2009 IEEE International Conference on Technologies for Practical Robot Applications
http://linked.open...in/vavai/riv/obor	JC
http://linked.open...ichTvurcuVysledku	4 (xsd:int)
http://linked.open...cetTvurcuVysledku	4 (xsd:int)
http://linked.open...vavai/riv/projekt	A System for robotic e-learning Robotic Evolutionary Self-Programming and Self-Assembling Organisms
http://linked.open...UplatneniVysledku	2009
http://linked.open...iv/tvurceVysledku	Faigl, Jan Krajník, Tomáš Přeučil, Libor Šváb, Jan
http://linked.open...vavai/riv/typAkce	WRD - Světová
http://linked.open...ain/vavai/riv/wos	000289878100007
http://linked.open.../riv/zahajeniAkce	2009-11-09 (xsd:date)
http://linked.open...n/vavai/riv/zamer	Decision Making and Control for Manufacturing III
number of pages	7 (xsd:int)
http://bibframe.org/vocab/doi	10.1109/TEPRA.2009.5339646
http://purl.org/ne...btex#hasPublisher	IEEE
https://schema.org/isbn	978-1-4244-4991-0
http://localhost/t...ganizacniJednotka	21230
is http://linked.open...avai/riv/vysledek of	FPGA-based Speeded Up Robust Features

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