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Description
| - This paper presents a design methodology for a hybrid Hardware-in-the-Loop (HIL) tester tool, based on both discrete event system theory, given by timed automata, and continuous systems theory, given by difference equations. It is implemented using an FPGA platform that guarantees speed enhancement, time accuracy and extensibility with no performance loss. We have focused on the implementation of a discrete event system, specifically timed automata into FPGA, and we have linked them with continuous systems implemented as filters in fixed point arithmetic. The paper shows a methodology, which employs widely used tools (Matlab, UPPAAL) as a user interface, and which implements the FPGA based tester tool.
- This paper presents a design methodology for a hybrid Hardware-in-the-Loop (HIL) tester tool, based on both discrete event system theory, given by timed automata, and continuous systems theory, given by difference equations. It is implemented using an FPGA platform that guarantees speed enhancement, time accuracy and extensibility with no performance loss. We have focused on the implementation of a discrete event system, specifically timed automata into FPGA, and we have linked them with continuous systems implemented as filters in fixed point arithmetic. The paper shows a methodology, which employs widely used tools (Matlab, UPPAAL) as a user interface, and which implements the FPGA based tester tool. (en)
- Článek prezentuje nástroj pro testování hybridních systémů v uzavřené smyčce. Spojitá část systému je reprezentována pomocí diferenčních rovnic a část sytému diskrétních událostí je reprezentována časovanými automaty. Nástroj je implementován pomocí konfigurovatelných hradlových polí (FPGA) zajišťujících rychlost, časovou determinističnost a snadnou rozšiřitelnost. (cs)
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Title
| - FPGA Based Tester Tool for Hybrid Real-Time Systems
- FPGA Testovaci nastroj pro hybridnich systemy realneho casu (cs)
- FPGA Based Tester Tool for Hybrid Real-Time Systems (en)
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skos:prefLabel
| - FPGA Based Tester Tool for Hybrid Real-Time Systems
- FPGA Testovaci nastroj pro hybridnich systemy realneho casu (cs)
- FPGA Based Tester Tool for Hybrid Real-Time Systems (en)
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skos:notation
| - RIV/68407700:21230/08:03146822!RIV09-MPO-21230___
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http://linked.open...avai/riv/aktivita
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http://linked.open...avai/riv/aktivity
| - P(FT-TA3/044), Z(MSM6840770038)
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http://linked.open...iv/cisloPeriodika
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http://linked.open...vai/riv/dodaniDat
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http://linked.open...aciTvurceVysledku
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http://linked.open.../riv/druhVysledku
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http://linked.open...iv/duvernostUdaju
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http://linked.open...titaPredkladatele
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http://linked.open...dnocenehoVysledku
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http://linked.open...ai/riv/idVysledku
| - RIV/68407700:21230/08:03146822
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http://linked.open...riv/jazykVysledku
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http://linked.open.../riv/klicovaSlova
| - FPGA; Hardware-in-the-Loop; Hybrid system; Model checking; Real-time system testing; System control; Timed automata (en)
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http://linked.open.../riv/klicoveSlovo
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http://linked.open...odStatuVydavatele
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http://linked.open...ontrolniKodProRIV
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http://linked.open...i/riv/nazevZdroje
| - MICROPROCESSORS AND MICROSYSTEMS - EMBEDDED HARDWARE DESIGN
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http://linked.open...in/vavai/riv/obor
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http://linked.open...ichTvurcuVysledku
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http://linked.open...cetTvurcuVysledku
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http://linked.open...vavai/riv/projekt
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http://linked.open...UplatneniVysledku
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http://linked.open...v/svazekPeriodika
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http://linked.open...iv/tvurceVysledku
| - Hanzálek, Zdeněk
- Krákora, Jan
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http://linked.open...ain/vavai/riv/wos
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http://linked.open...n/vavai/riv/zamer
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issn
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number of pages
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http://localhost/t...ganizacniJednotka
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is http://linked.open...avai/riv/vysledek
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