About: Scheduling of a LQ Control Algorithm for Efficient FPGA Implementation

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An Entity of Type : http://linked.opendata.cz/ontology/domain/vavai/Vysledek, within Data Space : linked.opendata.cz associated with source document(s)

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rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	This paper deals with the speed optimization of iterative algorithms with matrix operations or nested loops for hardware implementation in Field Programmable Gate Arrays (FPGA). The presented scheduling algorithm use Integer Linear Programming (ILP) while complex algorithm structure is modeled by system of linear inequalities. The method is demonstrated on a LQ control algorithm. An advantage of the presented scheduling method is its suitability for algorithms with longer iteration period. This paper deals with the speed optimization of iterative algorithms with matrix operations or nested loops for hardware implementation in Field Programmable Gate Arrays (FPGA). The presented scheduling algorithm use Integer Linear Programming (ILP) while complex algorithm structure is modeled by system of linear inequalities. The method is demonstrated on a LQ control algorithm. An advantage of the presented scheduling method is its suitability for algorithms with longer iteration period. (en)
Title	Scheduling of a LQ Control Algorithm for Efficient FPGA Implementation Scheduling of a LQ Control Algorithm for Efficient FPGA Implementation (en)
skos:prefLabel	Scheduling of a LQ Control Algorithm for Efficient FPGA Implementation Scheduling of a LQ Control Algorithm for Efficient FPGA Implementation (en)
skos:notation	RIV/68407700:21230/08:00146273!RIV12-MSM-21230___
http://linked.open...avai/riv/aktivita	Z
http://linked.open...avai/riv/aktivity	Z(MSM6840770038)
http://linked.open...vai/riv/dodaniDat	2012
http://linked.open...aciTvurceVysledku	Hanzálek, Zdeněk Šůcha, Přemysl
http://linked.open.../riv/druhVysledku	O - Ostatní výsledky nezařaditelné do žádného z výše uvedených druhů výsledku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	České vysoké učení technické v Praze / Fakulta elektrotechnická
http://linked.open...dnocenehoVysledku	393861
http://linked.open...ai/riv/idVysledku	RIV/68407700:21230/08:00146273
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	FPGA; cyclic scheduling; integer linear programming; modulo scheduling (en)
http://linked.open.../riv/klicoveSlovo	integer linear programming FPGA cyclic scheduling modulo scheduling
http://linked.open...ontrolniKodProRIV	[BB4132982A8E]
http://linked.open...in/vavai/riv/obor	JC
http://linked.open...ichTvurcuVysledku	2 (xsd:int)
http://linked.open...cetTvurcuVysledku	2 (xsd:int)
http://linked.open...UplatneniVysledku	2008
http://linked.open...iv/tvurceVysledku	Hanzálek, Zdeněk Šůcha, Přemysl
http://linked.open...n/vavai/riv/zamer	Decision Making and Control for Manufacturing III
http://localhost/t...ganizacniJednotka	21230

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