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  • This paper presents an integer linear programming (ILP) model for cyclic scheduling of tasks with unit processing time. Our work is motivated by digital signal processing (DSP) applications on FPGA (Field-Programmable Gate Array) architectures hosting several kinds of identical arithmetic units. These hardware resources can be formalized as dedicated sets of parallel identical processors. We propose a method to find an optimal periodic schedule of DSP algorithms on such architectures. The accent is put on the efficiency of the ILP model. We show advantages of the model in comparison with common ILP model on benchmarks and randomly generated instances.
  • This paper presents an integer linear programming (ILP) model for cyclic scheduling of tasks with unit processing time. Our work is motivated by digital signal processing (DSP) applications on FPGA (Field-Programmable Gate Array) architectures hosting several kinds of identical arithmetic units. These hardware resources can be formalized as dedicated sets of parallel identical processors. We propose a method to find an optimal periodic schedule of DSP algorithms on such architectures. The accent is put on the efficiency of the ILP model. We show advantages of the model in comparison with common ILP model on benchmarks and randomly generated instances. (en)
Title
  • Cyclic Scheduling of Tasks with Unit Processing Time on Dedicated Sets of Parallel Identical Processors
  • Cyclic Scheduling of Tasks with Unit Processing Time on Dedicated Sets of Parallel Identical Processors (en)
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  • Cyclic Scheduling of Tasks with Unit Processing Time on Dedicated Sets of Parallel Identical Processors
  • Cyclic Scheduling of Tasks with Unit Processing Time on Dedicated Sets of Parallel Identical Processors (en)
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  • RIV/68407700:21230/07:00133533!RIV12-MSM-21230___
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  • RIV/68407700:21230/07:00133533
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  • Cyclic Scheduling; Digital Signal Processing Applications; Multi-processor Scheduling (en)
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  • [E6646C006E8C]
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  • Hanzálek, Zdeněk
  • Šůcha, Přemysl
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  • 21230
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