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  • We introduce architecture of an arithmetic unit that is based on continued fractions and allows computing any linear rational function of two variables, including basic arithmetic operations like addition, subtraction, multiplication and division. Such a unit can easily exploit the parallel nature of continued fraction arithmetic and accelerate the otherwise low performance of its software implementation. The proposed architecture uses continued logarithms, which are an adapted variant of continued fractions and which suit hardware implementation more naturally through their bit-level granularity. We have used FPGA to implement such a unit and we present here some experimental results, which demonstrate promising properties of the proposed architecture.
  • We introduce architecture of an arithmetic unit that is based on continued fractions and allows computing any linear rational function of two variables, including basic arithmetic operations like addition, subtraction, multiplication and division. Such a unit can easily exploit the parallel nature of continued fraction arithmetic and accelerate the otherwise low performance of its software implementation. The proposed architecture uses continued logarithms, which are an adapted variant of continued fractions and which suit hardware implementation more naturally through their bit-level granularity. We have used FPGA to implement such a unit and we present here some experimental results, which demonstrate promising properties of the proposed architecture. (en)
  • Článek popisuje architekturu aritmetické jednotky založené na řetězových zlomcích. Tato jednotka umožňuje výpočet libovolné racionální lomené funkce dvou proměnných a tedy i základních aritmetických operací (součet, rozdíl, násobení, dělení). Hardwarová realizace této jednotky umožňuje využít paralelizmu řetězových zlomků a výrazně tak urychlit jejich výpočty. Navržená architektura využívá konkrétní formu řetězových zlomků v podobě řetězových logaritmů, jejichž hlavní výhodou je bitová granularita. K implementaci bylo použito FPGA obvodu - výsledky ukazují na výborné vlastnosti navržené architektury. (cs)
Title
  • Arithmetic Unit Based on Continued Fractions
  • Arithmetic Unit Based on Continued Fractions (en)
  • Aritmetická jednotka na bázi řetězových zlomků (cs)
skos:prefLabel
  • Arithmetic Unit Based on Continued Fractions
  • Arithmetic Unit Based on Continued Fractions (en)
  • Aritmetická jednotka na bázi řetězových zlomků (cs)
skos:notation
  • RIV/68407700:21230/06:03120768!RIV07-MSM-21230___
http://linked.open.../vavai/riv/strany
  • 225 ; 230
http://linked.open...avai/riv/aktivita
http://linked.open...avai/riv/aktivity
  • Z(MSM6840770014)
http://linked.open...vai/riv/dodaniDat
http://linked.open...aciTvurceVysledku
http://linked.open.../riv/druhVysledku
http://linked.open...iv/duvernostUdaju
http://linked.open...titaPredkladatele
http://linked.open...dnocenehoVysledku
  • 466033
http://linked.open...ai/riv/idVysledku
  • RIV/68407700:21230/06:03120768
http://linked.open...riv/jazykVysledku
http://linked.open.../riv/klicovaSlova
  • FPGA; computer arithmetic; continued fractions; hardware (en)
http://linked.open.../riv/klicoveSlovo
http://linked.open...ontrolniKodProRIV
  • [F495C2D424F1]
http://linked.open...v/mistoKonaniAkce
  • Herl'any
http://linked.open...i/riv/mistoVydani
  • Košice
http://linked.open...i/riv/nazevZdroje
  • Proceedings of the Seventh International Scientific Conference on Electronic Computers and Informatics ECI 2006
http://linked.open...in/vavai/riv/obor
http://linked.open...ichTvurcuVysledku
http://linked.open...cetTvurcuVysledku
http://linked.open...UplatneniVysledku
http://linked.open...iv/tvurceVysledku
  • Brabec, Tomáš
  • Lórencz, Róbert
http://linked.open...vavai/riv/typAkce
http://linked.open.../riv/zahajeniAkce
http://linked.open...n/vavai/riv/zamer
number of pages
http://purl.org/ne...btex#hasPublisher
  • Technická univerzita v Košiciach
https://schema.org/isbn
  • 80-8073-598-0
http://localhost/t...ganizacniJednotka
  • 21230
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