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  • In this work we are describing hardware implementation of Kohonen Self-Organizing Map. The essential feature of that kind of artificial neural networks is that they have ability to visualize data, i.e. transform data from n-dimensional data vectors into two dimensional map. We use this feature for facilitating neurologist diagnosis and prognosis. Having used the KSOM for speech signal processing, we came up against the challenging complexity and time-consuming characters of training and classification. Our motivation was to find a modification suitable for hardware implementation of Kohonen maps. We examined existing neurocomputers and decided to work out our own neurocomputer with a different, more suitable architecture. Our neurocomputer is being realized on FPGA. VHDL has been selected for the hardware description. Presented neurocomputer can be easily modified and simulated on personal computer with free available development tools for VHDL.
  • In this work we are describing hardware implementation of Kohonen Self-Organizing Map. The essential feature of that kind of artificial neural networks is that they have ability to visualize data, i.e. transform data from n-dimensional data vectors into two dimensional map. We use this feature for facilitating neurologist diagnosis and prognosis. Having used the KSOM for speech signal processing, we came up against the challenging complexity and time-consuming characters of training and classification. Our motivation was to find a modification suitable for hardware implementation of Kohonen maps. We examined existing neurocomputers and decided to work out our own neurocomputer with a different, more suitable architecture. Our neurocomputer is being realized on FPGA. VHDL has been selected for the hardware description. Presented neurocomputer can be easily modified and simulated on personal computer with free available development tools for VHDL. (en)
Title
  • An Accelerator for Kohonen Self-Organizing Maps
  • An Accelerator for Kohonen Self-Organizing Maps (en)
skos:prefLabel
  • An Accelerator for Kohonen Self-Organizing Maps
  • An Accelerator for Kohonen Self-Organizing Maps (en)
skos:notation
  • RIV/68407700:21230/06:00126094!RIV11-MSM-21230___
http://linked.open...avai/riv/aktivita
http://linked.open...avai/riv/aktivity
  • Z(MSM6840770012)
http://linked.open...vai/riv/dodaniDat
http://linked.open...aciTvurceVysledku
http://linked.open.../riv/druhVysledku
http://linked.open...iv/duvernostUdaju
http://linked.open...titaPredkladatele
http://linked.open...dnocenehoVysledku
  • 464741
http://linked.open...ai/riv/idVysledku
  • RIV/68407700:21230/06:00126094
http://linked.open...riv/jazykVysledku
http://linked.open.../riv/klicovaSlova
  • ANN; FPGA; KSOM; accelerator; self-organizing maps; speech (en)
http://linked.open.../riv/klicoveSlovo
http://linked.open...ontrolniKodProRIV
  • [DF9BBD1B521C]
http://linked.open...v/mistoKonaniAkce
  • Žilina
http://linked.open...i/riv/mistoVydani
  • Žilina
http://linked.open...i/riv/nazevZdroje
  • Digital Technologies 2006 - 3rd International Workshop
http://linked.open...in/vavai/riv/obor
http://linked.open...ichTvurcuVysledku
http://linked.open...cetTvurcuVysledku
http://linked.open...UplatneniVysledku
http://linked.open...iv/tvurceVysledku
  • Tučková, Jana
  • Šťastný, Jakub
  • Bártů, Marek
http://linked.open...vavai/riv/typAkce
http://linked.open.../riv/zahajeniAkce
http://linked.open...n/vavai/riv/zamer
number of pages
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  • Žilinská univerzita v Žiline. Elektrotechnická fakulta
https://schema.org/isbn
  • 80-8070-637-9
http://localhost/t...ganizacniJednotka
  • 21230
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