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  • Every modern CPU use a complex memory hierarchy, which consists of levels of cache memories. It is really difficult to predict the behavior of this hierarchy for the given program. The situation is even worse in SMP (symmetric multiprocessing) systems. The Cache emulator (shortly CE) can simulates the behavior of caches inside SMP system and compute the number of cache misses during a computation. All measurements are done in the %22off-line%22 mode on the one CPU; the CE uses own virtual cache memory for the exact simulation. It also means that another CPU activity doesn't influence the behavior of the CE.
  • Every modern CPU use a complex memory hierarchy, which consists of levels of cache memories. It is really difficult to predict the behavior of this hierarchy for the given program. The situation is even worse in SMP (symmetric multiprocessing) systems. The Cache emulator (shortly CE) can simulates the behavior of caches inside SMP system and compute the number of cache misses during a computation. All measurements are done in the %22off-line%22 mode on the one CPU; the CE uses own virtual cache memory for the exact simulation. It also means that another CPU activity doesn't influence the behavior of the CE. (en)
  • Každý moderní procesor obsahuje složitou paměťovou hierarchii, která zahrnuje i několik úrovní skrytých pamětí. Je velmi složité předpovědět chování této hierarchie pro daný program. Situace se dále komplikuje pro SMP systémy. Emulátor skrytých pamětí (CE) může simulovat chování skrytých pamětí v rámci SMP systému a spočítat počet výpadků během výpočtu. Měření jsou prováděna %22off-line%22 a na jednom procesoru; CE používá vlastní paměť pro přesnou simulaci. To znamená že ostatní procesy neovlivňují činnost CE. (cs)
Title
  • Cache Emulator for SMP Systems
  • Cache Emulator for SMP Systems (en)
  • Emulátor skrytých pamětí pro SMP systémy (cs)
skos:prefLabel
  • Cache Emulator for SMP Systems
  • Cache Emulator for SMP Systems (en)
  • Emulátor skrytých pamětí pro SMP systémy (cs)
skos:notation
  • RIV/68407700:21110/06:03114522!RIV07-AV0-21110___
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  • cache emulator; cache model; symmetric multiprocessing (en)
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  • Šimeček, Ivan
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