About: Computation and Communication Blocks for Xilinx Kintex7 FPGA with UTIA EdkDSP Accelerators. Vivado 2013.4 Designs with SW Demos

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About: Computation and Communication Blocks for Xilinx Kintex7 FPGA with UTIA EdkDSP Accelerators. Vivado 2013.4 Designs with SW Demos Goto Sponge NotDistinct Permalink

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rdfs:seeAlso	http://sp.utia.cz/index.php?ids=results&id=Utia_EdkDSP_Vivado_2013_4_KC705
Description	This application note describes the precompiled Vivado 2013.4 Kintex7 designs with the floating point EdkDSP accelerators and examples of use of basic communication and computation blocks used in the video processing and image processing applications. The MicroBlaze SoC design with the AXI bus is based on the Xilinx BIST (build in self-test) provided by Xilinx for the Kintex7 KC705 board and the Vivado 2014.3 design flow. The network HW controller is supporting 1Gbit/100Mbit/10Mbit standards with HW DMA and a SW stack based on the lwIP library described in the Xilinx application note XAPP1026. The MicroBlaze processor is controlling 8 EdkDSP floating point accelerators. Each accelerator is organised as 8xSIMD reconfigurable data path, controlled by a PicoBlaze6 controller. This evaluation package is provided by UTIA for the Xilinx KC705 board with the 28nm Kintex7 xc7k325t-2 FPGA part. This application note describes the precompiled Vivado 2013.4 Kintex7 designs with the floating point EdkDSP accelerators and examples of use of basic communication and computation blocks used in the video processing and image processing applications. The MicroBlaze SoC design with the AXI bus is based on the Xilinx BIST (build in self-test) provided by Xilinx for the Kintex7 KC705 board and the Vivado 2014.3 design flow. The network HW controller is supporting 1Gbit/100Mbit/10Mbit standards with HW DMA and a SW stack based on the lwIP library described in the Xilinx application note XAPP1026. The MicroBlaze processor is controlling 8 EdkDSP floating point accelerators. Each accelerator is organised as 8xSIMD reconfigurable data path, controlled by a PicoBlaze6 controller. This evaluation package is provided by UTIA for the Xilinx KC705 board with the 28nm Kintex7 xc7k325t-2 FPGA part. (en)
Title	Computation and Communication Blocks for Xilinx Kintex7 FPGA with UTIA EdkDSP Accelerators. Vivado 2013.4 Designs with SW Demos Computation and Communication Blocks for Xilinx Kintex7 FPGA with UTIA EdkDSP Accelerators. Vivado 2013.4 Designs with SW Demos (en)
skos:prefLabel	Computation and Communication Blocks for Xilinx Kintex7 FPGA with UTIA EdkDSP Accelerators. Vivado 2013.4 Designs with SW Demos Computation and Communication Blocks for Xilinx Kintex7 FPGA with UTIA EdkDSP Accelerators. Vivado 2013.4 Designs with SW Demos (en)
skos:notation	RIV/67985556:_____/14:00438631!RIV15-MSM-67985556
http://linked.open...avai/riv/aktivita	P
http://linked.open...avai/riv/aktivity	P(7H14004)
http://linked.open...vai/riv/dodaniDat	2015
http://linked.open...aciTvurceVysledku	Kadlec, Jiří
http://linked.open.../riv/druhVysledku	G/B - Funkční vzorek
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...onomickeParametry	Ověření 1 G ethernetu, file systemu, TFTP a WWW serveru v kombinaci s platformou EdkDSP pro výpočty v plovoucí řádové čárce na prototypové desce KC705.
http://linked.open...titaPredkladatele	Ústav teorie informace a automatizace AV ČR, v. v. i.
http://linked.open...dnocenehoVysledku	8452
http://linked.open...ai/riv/idVysledku	RIV/67985556:_____/14:00438631
http://linked.open...terniIdentifikace	Utia_EdkDSP_Vivado_2013_4_KC705
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open...vai/riv/kategorie	A - Do 5 mil. Kč
http://linked.open.../riv/klicovaSlova	floating-point accelerator; programmable hardware; signal processing acceleration (en)
http://linked.open.../riv/klicoveSlovo	programmable hardware floating-point accelerator signal processing acceleration
http://linked.open...ontrolniKodProRIV	[FE486E8EBD6C]
http://linked.open.../licencniPoplatek	N - Poskytovatel licence na výsledek nepožaduje licenční poplatek
http://linked.open...in/vavai/riv/obor	JC
http://linked.open...ichTvurcuVysledku	1 (xsd:int)
http://linked.open...cetTvurcuVysledku	1 (xsd:int)
http://linked.open...vavai/riv/projekt	ALMARVI - Algorithms, Design Methods, and Many-Core Execution Platform for Low-Power Massive Data-Rate Video and Image Processing
http://linked.open...UplatneniVysledku	2014
http://linked.open...echnickeParametry	Demonstrátor dovolující připojení k 1G ethernet, generování www stránek a přenos souborů a použití akcelerátorů výpočtu v plovoucí řádové čárce s výkonem až 22,4 GFLOP/s na obvodu Xilinx KINTEX7 na prototypové desce KC705.
http://linked.open...iv/tvurceVysledku	Kadlec, Jiří
http://linked.open...avai/riv/vlastnik	Ústav teorie informace a automatizace AV ČR, v.v
http://linked.open...itiJinymSubjektem	P - Nabytí licence je nutné v některých případech

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