About: Composing Data-driven Circuits Using Handshake in the Clock-Synchronous Domain

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rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	We present a technique for modelling and synthesis of fine-grained data-driven circuits in the clock-synchronous hardware, such as the field programmable gate arrays (FPGA), called the Flow-Transfer Level (FTL). The distinguishing property of the FTL technique is that it does not rely on FIFO queues to handle flow synchronization between the components (called operators). The communication channels, called pipes, employ conceptually a two-state handshake protocol. The handshake behaviour of each operator is defined logically using dependency subgraphs that are symmetrical for producers and consumers. The original data-flow netlist of operators is transformed into a global control dependency graph. Cycles in dependency graphs are allowed as long as they do not constitute real data dependencies but only dependencies in promises of handshake completions. A method is given that recursively eliminates these cycles. We present a technique for modelling and synthesis of fine-grained data-driven circuits in the clock-synchronous hardware, such as the field programmable gate arrays (FPGA), called the Flow-Transfer Level (FTL). The distinguishing property of the FTL technique is that it does not rely on FIFO queues to handle flow synchronization between the components (called operators). The communication channels, called pipes, employ conceptually a two-state handshake protocol. The handshake behaviour of each operator is defined logically using dependency subgraphs that are symmetrical for producers and consumers. The original data-flow netlist of operators is transformed into a global control dependency graph. Cycles in dependency graphs are allowed as long as they do not constitute real data dependencies but only dependencies in promises of handshake completions. A method is given that recursively eliminates these cycles. (en)
Title	Composing Data-driven Circuits Using Handshake in the Clock-Synchronous Domain Composing Data-driven Circuits Using Handshake in the Clock-Synchronous Domain (en)
skos:prefLabel	Composing Data-driven Circuits Using Handshake in the Clock-Synchronous Domain Composing Data-driven Circuits Using Handshake in the Clock-Synchronous Domain (en)
skos:notation	RIV/67985556:_____/13:00391639!RIV14-AV0-67985556
http://linked.open...avai/predkladatel	Ústav teorie informace a automatizace AV ČR, v. v. i.
http://linked.open...avai/riv/aktivita	I
http://linked.open...avai/riv/aktivity	I
http://linked.open...vai/riv/dodaniDat	2014
http://linked.open...aciTvurceVysledku	Sýkora, Jaroslav
http://linked.open.../riv/druhVysledku	D - Článek ve sborníku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	Ústav teorie informace a automatizace AV ČR, v. v. i.
http://linked.open...dnocenehoVysledku	66502
http://linked.open...ai/riv/idVysledku	RIV/67985556:_____/13:00391639
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	clock-synchronous hardware; field programmable gate arrays; Flow-Transfer Level (en)
http://linked.open.../riv/klicoveSlovo	Flow-Transfer Level clock-synchronous hardware field programmable gate arrays
http://linked.open...ontrolniKodProRIV	[C533D680F42B]
http://linked.open...v/mistoKonaniAkce	Karlovy Vary
http://linked.open...i/riv/mistoVydani	Brno
http://linked.open...i/riv/nazevZdroje	Proceedings of the 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)
http://linked.open...in/vavai/riv/obor	JC
http://linked.open...ichTvurcuVysledku	1 (xsd:int)
http://linked.open...cetTvurcuVysledku	1 (xsd:int)
http://linked.open...UplatneniVysledku	2013
http://linked.open...iv/tvurceVysledku	Sýkora, Jaroslav
http://linked.open...vavai/riv/typAkce	WRD - Světová
http://linked.open.../riv/zahajeniAkce	2013-04-08 (xsd:date)
number of pages	4 (xsd:int)
http://purl.org/ne...btex#hasPublisher	IEEE
https://schema.org/isbn	978-1-4673-6133-0

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