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Description
  • Článek prezentuje postup rozvržení algoritmu pro knihovnu aritmetických operací na FPGA. Jako příklad je uveden RLS lattice filter aplikovaný na potlačování šumu. Cílem je najít optimální cyklický rozvrh operací který vyhovuje požadavku na výkon filtru. Řešením úlohy je převod na jednoprocesorové cyklické rozvrkhování. Bulo dokázáno, že úloha NP úplná a bylo nalezeno optimální řešení pomocí celočíselného lineárního programování. Aplikace potlačování šumu je přímou demonstrací navrženého postupu. (cs)
  • This paper presents a scheduling technique for library of arithmetic logarithmic modules for FPGA illustrated on RLS filter for active noise cancellation. The problem under assumption is to find an optimal periodic cyclic schedule satisfying the timing constraints. The approach is based on transformation to monoprocessor cyclic scheduling with precedence delays. We prove that this problem is NP-hard and we suggest solution using Integer Linear Programming where moreover iteration overlapping or Cmax can be minimized. Results of optimized application show the utility of this approach.
  • This paper presents a scheduling technique for library of arithmetic logarithmic modules for FPGA illustrated on RLS filter for active noise cancellation. The problem under assumption is to find an optimal periodic cyclic schedule satisfying the timing constraints. The approach is based on transformation to monoprocessor cyclic scheduling with precedence delays. We prove that this problem is NP-hard and we suggest solution using Integer Linear Programming where moreover iteration overlapping or Cmax can be minimized. Results of optimized application show the utility of this approach. (en)
Title
  • Scheduling of iterative algorithms on FPGA with pipelined arithmetic unit
  • Rozvrhování iterativních algoritmů pro zřetězené aritmetické jednotky na FPGA (cs)
  • Scheduling of iterative algorithms on FPGA with pipelined arithmetic unit (en)
skos:prefLabel
  • Scheduling of iterative algorithms on FPGA with pipelined arithmetic unit
  • Rozvrhování iterativních algoritmů pro zřetězené aritmetické jednotky na FPGA (cs)
  • Scheduling of iterative algorithms on FPGA with pipelined arithmetic unit (en)
skos:notation
  • RIV/67985556:_____/04:00316662!RIV09-MSM-67985556
http://linked.open...avai/riv/aktivita
http://linked.open...avai/riv/aktivity
  • P(LN00B096), Z(AV0Z1075907)
http://linked.open...vai/riv/dodaniDat
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  • 585533
http://linked.open...ai/riv/idVysledku
  • RIV/67985556:_____/04:00316662
http://linked.open...riv/jazykVysledku
http://linked.open.../riv/klicovaSlova
  • cyclic scheduling; monoprocessor; iterative algorithms; integer linear programming; FPGA (en)
http://linked.open.../riv/klicoveSlovo
http://linked.open...ontrolniKodProRIV
  • [E5D49BA7363A]
http://linked.open...v/mistoKonaniAkce
  • Toronto
http://linked.open...i/riv/mistoVydani
  • Washington DC
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  • Real-Time and Embedded Technology and Applications Symposium
http://linked.open...in/vavai/riv/obor
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http://linked.open...vavai/riv/projekt
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http://linked.open...iv/tvurceVysledku
  • Hanzálek, Zdeněk
  • Pohl, Zdeněk
  • Šůcha, P.
http://linked.open...vavai/riv/typAkce
http://linked.open...ain/vavai/riv/wos
  • 000222239400045
http://linked.open.../riv/zahajeniAkce
http://linked.open...n/vavai/riv/zamer
number of pages
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  • IEEE Computer Society
https://schema.org/isbn
  • 0-7695-2148-7
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