About: FPGA implementation of logarithmic unit core.

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About: FPGA implementation of logarithmic unit core. Goto Sponge NotDistinct Permalink

An Entity of Type : http://linked.opendata.cz/ontology/domain/vavai/Vysledek, within Data Space : linked.opendata.cz associated with source document(s)

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rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	Implementation of floatig point in FPGA (Field Programmable Gate Arrays) is not easy. Paper presents FPGA core which implements these operations by representation of floating point numbers as 32-bit integer (fixed point) logarithm. Basic arithmetical operations are performed in the logarithm numbering system (LNS) suitable for FPGA. First, we describe Matlab library emulating bit-exactly the properties of the final hardware. Implementation of floatig point in FPGA (Field Programmable Gate Arrays) is not easy. Paper presents FPGA core which implements these operations by representation of floating point numbers as 32-bit integer (fixed point) logarithm. Basic arithmetical operations are performed in the logarithm numbering system (LNS) suitable for FPGA. First, we describe Matlab library emulating bit-exactly the properties of the final hardware. (en)
Title	FPGA implementation of logarithmic unit core. FPGA implementation of logarithmic unit core. (en)
skos:prefLabel	FPGA implementation of logarithmic unit core. FPGA implementation of logarithmic unit core. (en)
skos:notation	RIV/67985556:_____/01:16010114!RIV/2003/AV0/A16003/N
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http://linked.open...avai/riv/aktivita	Z
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http://linked.open...vai/riv/dodaniDat	2003
http://linked.open...aciTvurceVysledku	Matoušek, Rudolf Líčko, Miroslav Kadlec, Jiří
http://linked.open.../riv/druhVysledku	D - Článek ve sborníku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	Ústav teorie informace a automatizace AV ČR, v. v. i.
http://linked.open...dnocenehoVysledku	680693
http://linked.open...ai/riv/idVysledku	RIV/67985556:_____/01:16010114
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	field programmable gate array (en)
http://linked.open.../riv/klicoveSlovo	field programmable gate array
http://linked.open...ontrolniKodProRIV	[D4BF79E71E58]
http://linked.open...v/mistoKonaniAkce	Nürnberg [DE]
http://linked.open...i/riv/mistoVydani	Nürnberg
http://linked.open...i/riv/nazevZdroje	Embedded Intelligence 2001.
http://linked.open...in/vavai/riv/obor	JC
http://linked.open...ichTvurcuVysledku	3 (xsd:int)
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http://linked.open...ocetUcastnikuAkce	0 (xsd:int)
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http://linked.open...UplatneniVysledku	2001
http://linked.open...iv/tvurceVysledku	Kadlec, Jiří Matoušek, Rudolf Líčko, Miroslav
http://linked.open...vavai/riv/typAkce	WRD - Světová
http://linked.open.../riv/zahajeniAkce	2001-02-14 (xsd:date)
http://linked.open...n/vavai/riv/zamer	Uncertainty methods in theoretical cybernetics: system identification, information processing, decision-making, and control
number of pages	8 (xsd:int)
http://purl.org/ne...btex#hasPublisher	Design & Elektronik

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