About: Verifying VHDL Designs with Multiple Clocks in SMV

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An Entity of Type : http://linked.opendata.cz/ontology/domain/vavai/Vysledek, within Data Space : linked.opendata.cz associated with source document(s)

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rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	The paper considers the problem of model checking real-life VHDL- based hardware designs via their automated transformation to a model verifiable using the SMV model checker. In particular, model checking of asynchronous designs, i.e. designs driven by multiple clocks, is discussed. Two original approaches to compiling asynchronous VHDL designs to the SMV language such that errors possibly arising from the asynchronicity are preserved are proposed. The paper also presents results of experiments with using the proposed methods for verification of several real-life asynchronous components of an FPGA-based router being developed within the Liberouter project. The paper considers the problem of model checking real-life VHDL- based hardware designs via their automated transformation to a model verifiable using the SMV model checker. In particular, model checking of asynchronous designs, i.e. designs driven by multiple clocks, is discussed. Two original approaches to compiling asynchronous VHDL designs to the SMV language such that errors possibly arising from the asynchronicity are preserved are proposed. The paper also presents results of experiments with using the proposed methods for verification of several real-life asynchronous components of an FPGA-based router being developed within the Liberouter project. (en) Článek se zabývá problémem ověřování modelů reálných hardwarových systémů specifikovaných pomocí jazyka VHDL. Způsob verifikace je založen na překladu VHDL programů do jazyka Cadence SMV. Výsledky uvedené v tomto článku se zaměřují na reálnou verifikaci hardwarových obvodů s asynchronními komponentami. Článek uvádí dva přístupy včetně experimentálního ověření. (cs)
Title	Verifying VHDL Designs with Multiple Clocks in SMV Verifikace VHDL programů s více hodinami pomocí SMV (cs) Verifying VHDL Designs with Multiple Clocks in SMV (en)
skos:prefLabel	Verifying VHDL Designs with Multiple Clocks in SMV Verifikace VHDL programů s více hodinami pomocí SMV (cs) Verifying VHDL Designs with Multiple Clocks in SMV (en)
skos:notation	RIV/63839172:_____/07:00000636!RIV08-MSM-63839172
http://linked.open.../vavai/riv/strany	148;164
http://linked.open...avai/riv/aktivita	Z
http://linked.open...avai/riv/aktivity	Z(MSM6383917201)
http://linked.open...iv/cisloPeriodika	4346
http://linked.open...vai/riv/dodaniDat	2008
http://linked.open...aciTvurceVysledku	Šafránek, David Vojnar, Tomáš Matoušek, Petr Řehák, Vojtěch
http://linked.open.../riv/druhVysledku	J - Článek v odborném periodiku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	CESNET - zájmové sdružení právnických osob
http://linked.open...dnocenehoVysledku	457811
http://linked.open...ai/riv/idVysledku	RIV/63839172:_____/07:00000636
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	formal verification; model checking; VHDL; asynchronous clock domains (en)
http://linked.open.../riv/klicoveSlovo	VHDL model checking formal verification asynchronous clock domains
http://linked.open...odStatuVydavatele	DE - Spolková republika Německo
http://linked.open...ontrolniKodProRIV	[D21C78DE98BF]
http://linked.open...i/riv/nazevZdroje	Lecture Notes in Computer Science
http://linked.open...in/vavai/riv/obor	JC
http://linked.open...ichTvurcuVysledku	6 (xsd:int)
http://linked.open...cetTvurcuVysledku	6 (xsd:int)
http://linked.open...UplatneniVysledku	2007
http://linked.open...v/svazekPeriodika	2007
http://linked.open...iv/tvurceVysledku	Vojnar, Tomáš Šafránek, David Matoušek, Petr Řehák, Vojtěch
http://linked.open...n/vavai/riv/zamer	Optical National Research Network and Its New Applications
issn	0302-9743
number of pages	16 (xsd:int)
is http://linked.open...avai/riv/vysledek of	Verifying VHDL Designs with Multiple Clocks in SMV Verifying VHDL Designs with Multiple Clocks in SMV Verifying VHDL Designs with Multiple Clocks in SMV

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