About: RS 232 Compatible Duplex Serial Data Interface Circuit Design

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An Entity of Type : http://linked.opendata.cz/ontology/domain/vavai/Vysledek, within Data Space : linked.opendata.cz associated with source document(s)

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rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	The model of the RS 232C serial duplex interface of microcomputer is created in VHDL, and it is simulated in various modes of function. The additional function is used for error detection of data transmission. The asynchronous properties are evaluated inthe system implementation in various technologies. The model of the RS 232C serial duplex interface of microcomputer is created in VHDL, and it is simulated in various modes of function. The additional function is used for error detection of data transmission. The asynchronous properties are evaluated inthe system implementation in various technologies. (en)
Title	RS 232 Compatible Duplex Serial Data Interface Circuit Design RS 232 Compatible Duplex Serial Data Interface Circuit Design (en)
skos:prefLabel	RS 232 Compatible Duplex Serial Data Interface Circuit Design RS 232 Compatible Duplex Serial Data Interface Circuit Design (en)
skos:notation	RIV/61989100:27240/02:00006714!RIV/2003/GA0/272403/N
http://linked.open.../vavai/riv/strany	86 - 93
http://linked.open...avai/riv/aktivita	P
http://linked.open...avai/riv/aktivity	P(GA102/01/1531)
http://linked.open...vai/riv/dodaniDat	2003
http://linked.open...aciTvurceVysledku	Vlček, Karel
http://linked.open.../riv/druhVysledku	D - Článek ve sborníku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	Vysoká škola báňská - Technická univerzita Ostrava / Fakulta elektrotechniky a informatiky
http://linked.open...dnocenehoVysledku	662849
http://linked.open...ai/riv/idVysledku	RIV/61989100:27240/02:00006714
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	RS 232C model, VHDL, Asynchronous timetable simulation (en)
http://linked.open.../riv/klicoveSlovo	VHDL Asynchronous timetable simulation RS 232C model
http://linked.open...ontrolniKodProRIV	[1DE051F7CCCC]
http://linked.open...v/mistoKonaniAkce	Brno, CZ
http://linked.open...i/riv/mistoVydani	Brno
http://linked.open...i/riv/nazevZdroje	Proc. of STO-8
http://linked.open...in/vavai/riv/obor	JC
http://linked.open...ichTvurcuVysledku	1 (xsd:int)
http://linked.open...cetTvurcuVysledku	1 (xsd:int)
http://linked.open...ocetUcastnikuAkce	0 (xsd:int)
http://linked.open...nichUcastnikuAkce	0 (xsd:int)
http://linked.open...vavai/riv/projekt	Formal approaches in digital circuit diagnostics - testable design verification
http://linked.open...UplatneniVysledku	2002
http://linked.open...iv/tvurceVysledku	Vlček, Karel
http://linked.open...vavai/riv/typAkce	EUR - Evropská
http://linked.open.../riv/zahajeniAkce	2002-09-25 (xsd:date)
number of pages	8 (xsd:int)
http://purl.org/ne...btex#hasPublisher	VA v Brně
https://schema.org/isbn	80-214-2190-8
http://localhost/t...ganizacniJednotka	27240

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