About: An evaluation of the application dependent FPGA test method

Facets (new session)
Description
Metadata
Settings
- owl:sameAs
- Inference Rule:

About: An evaluation of the application dependent FPGA test method Goto Sponge NotDistinct Permalink

An Entity of Type : http://linked.opendata.cz/ontology/domain/vavai/Vysledek, within Data Space : linked.opendata.cz associated with source document(s)

Attributes	Values
rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
rdfs:seeAlso	http://apps.webofknowledge.com/full_record.do?product=WOS&search_mode=GeneralSearch&qid=10&SID=W1INN4fIFD5m8h3IIim&page=1&doc=2
Description	In this paper we evaluate the application dependent FPGA (Field Programmable Gate Array) test method which uses an ASIC BIST (Application Specific Integrated Circuit Built-in Self-Test) techniques and tools and efficiently utilizes the properties of nowadays FPGA devices, such as the partial runtime reconfiguration. The method splits the tested circuit and then uses partial reconfiguration to change the role of the partitioned modules, which may act as testers or as response analyzers. Circuit partitions are translated to an ATPG (Automatic Test Pattern Generator) readable format and the deterministic test vectors are generated. The compression tool is used to compress test patterns, thus it is not required to create additional test access interfaces or to use multiple reconfigurations. We show that the usage of the method reduces test time and memory requirements and it leads to good test coverage results. Each step of the design flow is described and evaluated in detail as well as the experimental results and the hardware. In this paper we evaluate the application dependent FPGA (Field Programmable Gate Array) test method which uses an ASIC BIST (Application Specific Integrated Circuit Built-in Self-Test) techniques and tools and efficiently utilizes the properties of nowadays FPGA devices, such as the partial runtime reconfiguration. The method splits the tested circuit and then uses partial reconfiguration to change the role of the partitioned modules, which may act as testers or as response analyzers. Circuit partitions are translated to an ATPG (Automatic Test Pattern Generator) readable format and the deterministic test vectors are generated. The compression tool is used to compress test patterns, thus it is not required to create additional test access interfaces or to use multiple reconfigurations. We show that the usage of the method reduces test time and memory requirements and it leads to good test coverage results. Each step of the design flow is described and evaluated in detail as well as the experimental results and the hardware. (en)
Title	An evaluation of the application dependent FPGA test method An evaluation of the application dependent FPGA test method (en)
skos:prefLabel	An evaluation of the application dependent FPGA test method An evaluation of the application dependent FPGA test method (en)
skos:notation	RIV/46747885:24220/12:#0002019!RIV13-MSM-24220___
http://linked.open...avai/predkladatel	Fakulta mechatroniky, informatiky a mezioborových studií
http://linked.open...avai/riv/aktivita	S
http://linked.open...avai/riv/aktivity	S
http://linked.open...vai/riv/dodaniDat	2013
http://linked.open...aciTvurceVysledku	Rozkovec, Martin Jeníček, J. Novák, Ondřej
http://linked.open.../riv/druhVysledku	D - Článek ve sborníku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	Technická univerzita v Liberci / Fakulta mechatroniky, informatiky a mezioborových studií
http://linked.open...dnocenehoVysledku	121955
http://linked.open...ai/riv/idVysledku	RIV/46747885:24220/12:#0002019
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	Field programmable gate arrays (en)
http://linked.open.../riv/klicoveSlovo	Field programmable gate arrays
http://linked.open...ontrolniKodProRIV	[80413C6989CD]
http://linked.open...v/mistoKonaniAkce	Tallinn, ESTONIA
http://linked.open...i/riv/nazevZdroje	Proceedings of the 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2012
http://linked.open...in/vavai/riv/obor	JC
http://linked.open...ichTvurcuVysledku	3 (xsd:int)
http://linked.open...cetTvurcuVysledku	3 (xsd:int)
http://linked.open...UplatneniVysledku	2012
http://linked.open...iv/tvurceVysledku	Jeníček, Jiří Novák, Ondřej Rozkovec, Martin
http://linked.open...vavai/riv/typAkce	WRD - Světová
http://linked.open...ain/vavai/riv/wos	000312905700011
http://linked.open.../riv/zahajeniAkce	2012-04-18 (xsd:date)
number of pages	4 (xsd:int)
http://bibframe.org/vocab/doi	10.1109/DDECS.2012.6219017
http://purl.org/ne...btex#hasPublisher	IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA
https://schema.org/isbn	978-1-4673-1187-8
http://localhost/t...ganizacniJednotka	24220
is http://linked.open...avai/riv/vysledek of	An evaluation of the application dependent FPGA test method

Faceted Search & Find service v1.16.118 as of Jun 21 2024

Alternative Linked Data Documents: ODE Content Formats:

RDF

ODATA

Microdata

About

OpenLink Virtuoso version 07.20.3240 as of Jun 21 2024, on Linux (x86_64-pc-linux-gnu), Single-Server Edition (126 GB total memory, 47 GB memory in use)
Data on this page belongs to its respective rights holders.
Virtuoso Faceted Browser Copyright © 2009-2024 OpenLink Software