About: On measurement of impact of the metallization and FPGA design to the changes of slice parameters and generation of delay faults (Stability of timing parameters of 45nm FPGA Spartan 6)

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About: On measurement of impact of the metallization and FPGA design to the changes of slice parameters and generation of delay faults (Stability of timing parameters of 45nm FPGA Spartan 6) Goto Sponge NotDistinct Permalink

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rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
rdfs:seeAlso	http://www.scopus.com
Description	The rapidly growing world of FPGA devices offers important as well as interesting platforms for analyses of process scaling. It creates also new study opportunities in case of new process variations and degradation effects. Changes in parameters of FPGAs in time or under either power supply voltage or temperature variations result in timing variations or delays and may affect the final design quality and dependability. Such timing variations may result in delay faults, up to the final device or equipment malfunction or failure. FPGA designs must be carefully tested and simulated during the design phase. This area is well-covered by many papers and publications and being investigated again with the new processes coming every approximately 2 years. This paper investigates the area of effects caused by the FPGA chip design and metallization or design trade-offs. The paper presents interesting results obtained during various tests including the important values of the total delays caused by neighboring loaded SLICEs or locations in the FPGA. These results were obtained by a method of frequency and delay measurement, capable of delivering stable results in the range of 0.1ps (100fs), using only inexpensive tools and methods. The rapidly growing world of FPGA devices offers important as well as interesting platforms for analyses of process scaling. It creates also new study opportunities in case of new process variations and degradation effects. Changes in parameters of FPGAs in time or under either power supply voltage or temperature variations result in timing variations or delays and may affect the final design quality and dependability. Such timing variations may result in delay faults, up to the final device or equipment malfunction or failure. FPGA designs must be carefully tested and simulated during the design phase. This area is well-covered by many papers and publications and being investigated again with the new processes coming every approximately 2 years. This paper investigates the area of effects caused by the FPGA chip design and metallization or design trade-offs. The paper presents interesting results obtained during various tests including the important values of the total delays caused by neighboring loaded SLICEs or locations in the FPGA. These results were obtained by a method of frequency and delay measurement, capable of delivering stable results in the range of 0.1ps (100fs), using only inexpensive tools and methods. (en)
Title	On measurement of impact of the metallization and FPGA design to the changes of slice parameters and generation of delay faults (Stability of timing parameters of 45nm FPGA Spartan 6) On measurement of impact of the metallization and FPGA design to the changes of slice parameters and generation of delay faults (Stability of timing parameters of 45nm FPGA Spartan 6) (en)
skos:prefLabel	On measurement of impact of the metallization and FPGA design to the changes of slice parameters and generation of delay faults (Stability of timing parameters of 45nm FPGA Spartan 6) On measurement of impact of the metallization and FPGA design to the changes of slice parameters and generation of delay faults (Stability of timing parameters of 45nm FPGA Spartan 6) (en)
skos:notation	RIV/46747885:24220/12:#0002015!RIV13-MSM-24220___
http://linked.open...avai/predkladatel	Fakulta mechatroniky, informatiky a mezioborových studií
http://linked.open...avai/riv/aktivita	S
http://linked.open...avai/riv/aktivity	S
http://linked.open...vai/riv/dodaniDat	2013
http://linked.open...aciTvurceVysledku	Plíva, Zdeněk Pfeifer, Petr
http://linked.open.../riv/druhVysledku	D - Článek ve sborníku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	Technická univerzita v Liberci / Fakulta mechatroniky, informatiky a mezioborových studií
http://linked.open...dnocenehoVysledku	156271
http://linked.open...ai/riv/idVysledku	RIV/46747885:24220/12:#0002015
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	Field programmable gate arrays (en)
http://linked.open.../riv/klicoveSlovo	Field programmable gate arrays
http://linked.open...ontrolniKodProRIV	[0AAFC031CB40]
http://linked.open...v/mistoKonaniAkce	Oslo
http://linked.open...i/riv/nazevZdroje	Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012
http://linked.open...in/vavai/riv/obor	JC
http://linked.open...ichTvurcuVysledku	2 (xsd:int)
http://linked.open...cetTvurcuVysledku	2 (xsd:int)
http://linked.open...UplatneniVysledku	2012
http://linked.open...iv/tvurceVysledku	Plíva, Zdeněk Pfeifer, Petr
http://linked.open...vavai/riv/typAkce	WRD - Světová
http://linked.open.../riv/zahajeniAkce	2012-08-29 (xsd:date)
number of pages	4 (xsd:int)
http://bibframe.org/vocab/doi	10.1109/FPL.2012.6339167
http://purl.org/ne...btex#hasPublisher	Neuveden
https://schema.org/isbn	978-1-4673-2257-7
http://localhost/t...ganizacniJednotka	24220
is http://linked.open...avai/riv/vysledek of	On measurement of impact of the metallization and FPGA design to the changes of slice parameters and generation of delay faults (Stability of timing parameters of 45nm FPGA Spartan 6)

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