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About:
Implementation of Dynamically Reconfigurable Test Archtecture for FPGA Circuits
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Description
The paper is about Implementation of Dynamically Reconfigurable Test Archtecture for FPGA Circuits
The paper is about Implementation of Dynamically Reconfigurable Test Archtecture for FPGA Circuits
(en)
Článek je o implementaci dynamicky rekonfigurovatelné testovací architektury pro FPGA obvody
(cs)
Title
Implementation of Dynamically Reconfigurable Test Archtecture for FPGA Circuits
Implementace dynamicky rekonfigurovatelné testovací architektury pro FPGA obvody
(cs)
Implementation of Dynamically Reconfigurable Test Archtecture for FPGA Circuits
(en)
skos:prefLabel
Implementation of Dynamically Reconfigurable Test Archtecture for FPGA Circuits
Implementace dynamicky rekonfigurovatelné testovací architektury pro FPGA obvody
(cs)
Implementation of Dynamically Reconfigurable Test Archtecture for FPGA Circuits
(en)
skos:notation
RIV/46747885:24220/08:#0001191!RIV09-AV0-24220___
http://linked.open...avai/riv/aktivita
P
http://linked.open...avai/riv/aktivity
P(1QS108040510)
http://linked.open...vai/riv/dodaniDat
2009
http://linked.open...aciTvurceVysledku
Rozkovec, Martin
http://linked.open.../riv/druhVysledku
D - Článek ve sborníku
http://linked.open...iv/duvernostUdaju
S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele
Technická univerzita v Liberci / Fakulta mechatroniky, informatiky a mezioborových studií
http://linked.open...dnocenehoVysledku
371624
http://linked.open...ai/riv/idVysledku
RIV/46747885:24220/08:#0001191
http://linked.open...riv/jazykVysledku
eng - angličtina
http://linked.open.../riv/klicovaSlova
FPGA
(en)
http://linked.open.../riv/klicoveSlovo
FPGA
http://linked.open...ontrolniKodProRIV
[E1DCF9EEB1D0]
http://linked.open...v/mistoKonaniAkce
Bratislava
http://linked.open...i/riv/mistoVydani
Slovakia
http://linked.open...i/riv/nazevZdroje
IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems
http://linked.open...in/vavai/riv/obor
JC
http://linked.open...ichTvurcuVysledku
1
(
xsd:int
)
http://linked.open...cetTvurcuVysledku
1
(
xsd:int
)
http://linked.open...vavai/riv/projekt
Technology for improving the testability of modern digital circuits
http://linked.open...UplatneniVysledku
2008
http://linked.open...iv/tvurceVysledku
Rozkovec, M.
http://linked.open...vavai/riv/typAkce
WRD - Světová
http://linked.open...ain/vavai/riv/wos
000256936300039
http://linked.open.../riv/zahajeniAkce
2008-01-01
(
xsd:date
)
number of pages
5
(
xsd:int
)
http://purl.org/ne...btex#hasPublisher
IEEE
https://schema.org/isbn
978-1-4244-2276-0
http://localhost/t...ganizacniJednotka
24220
is
http://linked.open...avai/riv/vysledek
of
Implementation of Dynamically Reconfigurable Test Archtecture for FPGA Circuits
Implementation of Dynamically Reconfigurable Test Archtecture for FPGA Circuits
Implementation of Dynamically Reconfigurable Test Archtecture for FPGA Circuits
Implementation of Dynamically Reconfigurable Test Archtecture for FPGA Circuits
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