About: Optimization of the bond and etch-back silicon-on-insulator manufacturing processes

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rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	We have studied the bond and etch-back silicon on insulator (BESOI) manufacturing processes. The top silicon layer, called device layer, was studied from its epitaxial growth on 2 um thick SiGeB etch-stop layer, through 850C/12 h bond strengthening annealing and selective etching, to the ﬁnal chemical-mechanical planarization (CMP) treatment. We have found that the device layer thickness is reduced during the annealing and selective tetramethylamonium hydroxide and HNA (mixture of hydroﬂuoric, nitric and acetic acids) etching processes. This thickness reduction was found to be 0.592 um, independently on the original device layer thickness. We have also found that the wafer surface is covered by a thin silicon suboxide layer after the HNA etching. The layer can be however easily removed by CMP with stock removal higher than 0.1um. Such process also polishes the wafer surface to prime quality micro-roughness. For studied BESOI process we therefore propose additional epitaxial growth of 0.8 um to the thickness target of the lightly doped epitaxial layer (future device layer) and using CMP stock removal of 0.2 um to obtain BESOI wafer with superior device layer surface micro-roughness and thickness uniformity. We have studied the bond and etch-back silicon on insulator (BESOI) manufacturing processes. The top silicon layer, called device layer, was studied from its epitaxial growth on 2 um thick SiGeB etch-stop layer, through 850C/12 h bond strengthening annealing and selective etching, to the ﬁnal chemical-mechanical planarization (CMP) treatment. We have found that the device layer thickness is reduced during the annealing and selective tetramethylamonium hydroxide and HNA (mixture of hydroﬂuoric, nitric and acetic acids) etching processes. This thickness reduction was found to be 0.592 um, independently on the original device layer thickness. We have also found that the wafer surface is covered by a thin silicon suboxide layer after the HNA etching. The layer can be however easily removed by CMP with stock removal higher than 0.1um. Such process also polishes the wafer surface to prime quality micro-roughness. For studied BESOI process we therefore propose additional epitaxial growth of 0.8 um to the thickness target of the lightly doped epitaxial layer (future device layer) and using CMP stock removal of 0.2 um to obtain BESOI wafer with superior device layer surface micro-roughness and thickness uniformity. (en)
Title	Optimization of the bond and etch-back silicon-on-insulator manufacturing processes Optimization of the bond and etch-back silicon-on-insulator manufacturing processes (en)
skos:prefLabel	Optimization of the bond and etch-back silicon-on-insulator manufacturing processes Optimization of the bond and etch-back silicon-on-insulator manufacturing processes (en)
skos:notation	RIV/26821532:_____/13:#0000034!RIV13-TA0-26821532
http://linked.open...avai/predkladatel	ON SEMICONDUCTOR CZECH REPUBLIC, s.r.o., právní nástupce
http://linked.open...avai/riv/aktivita	P
http://linked.open...avai/riv/aktivity	P(TA01010078)
http://linked.open...iv/cisloPeriodika	6
http://linked.open...vai/riv/dodaniDat	2013
http://linked.open...aciTvurceVysledku	Kostelník, Petr Šik, Jan
http://linked.open.../riv/druhVysledku	J - Článek v odborném periodiku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	ON SEMICONDUCTOR CZECH REPUBLIC, s.r.o.
http://linked.open...dnocenehoVysledku	94492
http://linked.open...ai/riv/idVysledku	RIV/26821532:_____/13:#0000034
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	SOI; Epitaxy; Selective Etching; CMP (en)
http://linked.open.../riv/klicoveSlovo	Epitaxy Selective Etching SOI CMP
http://linked.open...odStatuVydavatele	US - Spojené státy americké
http://linked.open...ontrolniKodProRIV	[7BB608519F63]
http://linked.open...i/riv/nazevZdroje	Advanced Science, Engineering and Medicine
http://linked.open...in/vavai/riv/obor	JJ
http://linked.open...ichTvurcuVysledku	2 (xsd:int)
http://linked.open...cetTvurcuVysledku	2 (xsd:int)
http://linked.open...vavai/riv/projekt	SOI Structures for Advanced Semiconductor Applications
http://linked.open...UplatneniVysledku	2013
http://linked.open...v/svazekPeriodika	5
http://linked.open...iv/tvurceVysledku	Kostelník, Petr Šik, Jan
issn	2164-6627
number of pages	5 (xsd:int)

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