About: Acceleration of Transistor-Level Evolution using Xilinx Zynq Platform

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An Entity of Type : http://linked.opendata.cz/ontology/domain/vavai/Vysledek, within Data Space : linked.opendata.cz associated with source document(s)

Attributes	Values
rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
rdfs:seeAlso	http://dx.doi.org/10.1109/ICES.2014.7008716
Description	The aim of this paper is to introduce a new acceleratordeveloped to address the problem of evolutionary synthesisof digital circuits at transistor level. The proposed accelerator,based on recently introduced Xilinx Zynq platform, consists ofa discrete simulator implemented in programmable logic and anevolutionary algorithm running on a tightly coupled embeddedARM processor. The discrete simulator was introduced in order toachieve a good trade-off between the precision and performanceof the simulation of transistor-level circuits. The simulator isimplemented using the concept of virtual reconfigurable circuitand operates on multiple logic levels which enables to evaluate thebehavior of candidate transistor-level circuits at a reasonable levelof detail. In this work, the concept of virtual reconfigurable circuitwas extended to enable bidirectional data flow which representsthe basic feature of transistor level circuits. According to theexperimental evaluation, the proposed architecture speed The aim of this paper is to introduce a new acceleratordeveloped to address the problem of evolutionary synthesisof digital circuits at transistor level. The proposed accelerator,based on recently introduced Xilinx Zynq platform, consists ofa discrete simulator implemented in programmable logic and anevolutionary algorithm running on a tightly coupled embeddedARM processor. The discrete simulator was introduced in order toachieve a good trade-off between the precision and performanceof the simulation of transistor-level circuits. The simulator isimplemented using the concept of virtual reconfigurable circuitand operates on multiple logic levels which enables to evaluate thebehavior of candidate transistor-level circuits at a reasonable levelof detail. In this work, the concept of virtual reconfigurable circuitwas extended to enable bidirectional data flow which representsthe basic feature of transistor level circuits. According to theexperimental evaluation, the proposed architecture speed (en)
Title	Acceleration of Transistor-Level Evolution using Xilinx Zynq Platform Acceleration of Transistor-Level Evolution using Xilinx Zynq Platform (en)
skos:prefLabel	Acceleration of Transistor-Level Evolution using Xilinx Zynq Platform Acceleration of Transistor-Level Evolution using Xilinx Zynq Platform (en)
skos:notation	RIV/00216305:26230/14:PU112083!RIV15-GA0-26230___
http://linked.open...avai/riv/aktivita	P
http://linked.open...avai/riv/aktivity	P(GA14-04197S)
http://linked.open...vai/riv/dodaniDat	2015
http://linked.open...aciTvurceVysledku	Vašíček, Zdeněk Mrázek, Vojtěch
http://linked.open.../riv/druhVysledku	D - Článek ve sborníku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	Vysoké učení technické v Brně / Fakulta informačních technologií
http://linked.open...dnocenehoVysledku	1401
http://linked.open...ai/riv/idVysledku	RIV/00216305:26230/14:PU112083
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	Xilinx Zynq, transistor-level evolution, evolutionary design, combinational circuit (en)
http://linked.open.../riv/klicoveSlovo	Xilinx Zynq evolutionary design combinational circuit transistor-level evolution
http://linked.open...ontrolniKodProRIV	[24681F5E9B60]
http://linked.open...v/mistoKonaniAkce	Orlando
http://linked.open...i/riv/mistoVydani	Piscataway
http://linked.open...i/riv/nazevZdroje	2014 IEEE International Conference on Evolvable Systems Proceedings
http://linked.open...in/vavai/riv/obor	IN
http://linked.open...ichTvurcuVysledku	2 (xsd:int)
http://linked.open...cetTvurcuVysledku	2 (xsd:int)
http://linked.open...vavai/riv/projekt	Advanced Methods for Evolutionary Design of Complex Digital Circuits
http://linked.open...UplatneniVysledku	2014
http://linked.open...iv/tvurceVysledku	Vašíček, Zdeněk Mrázek, Vojtěch
http://linked.open...vavai/riv/typAkce	WRD - Světová
http://linked.open.../riv/zahajeniAkce	2014-12-09 (xsd:date)
number of pages	8 (xsd:int)
http://bibframe.org/vocab/doi	10.1109/ICES.2014.7008716
http://purl.org/ne...btex#hasPublisher	Institute of Electrical and Electronics Engineers
https://schema.org/isbn	978-1-4799-4480-4
http://localhost/t...ganizacniJednotka	26230

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