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| rdfs:seeAlso
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| Description
| - ZyEHW is a joint hardware-software project for evolutionary design in the Xilinx Zynq-7000 field-programmable gate array. It contains (1) the hardware descriptions of the evolutionary design framework implemented in the programmable logic, (2) the software for both ARM processors of the Zynq platform and (3) the software required for generating the inputs and processing the outputs of the evolutionary design framework.The evolutionary design framework is based on our developed architecture where the candidate solutions can be established and mutated by fine-grained partial reconfiguration of look-up tables. Our advanced control unit and the reduced routing ensures that six candidate solutions can be evaluated in parallel (in a XC7Z020 device) and at a very high operational frequency (a larger device would allow to evaluate even more candidate solutions in parallel).The program code is deployed into one of the processors of Zynq-7000 and the evolutionary design framework into its programmable logic. Evolutionary on-line synthesis is performed by the other available processor. The functionality is transferred from software into hardware on-line, during runtime. This approach serves essentially the same purpose as high-level synthesis but the synthesis can be performed by a simple embedded computational platform and on-line.Version v1.0 of ZyEHW includes the complete implementation of the case study for image filter evolution (noise filtering and edge detection).
- ZyEHW is a joint hardware-software project for evolutionary design in the Xilinx Zynq-7000 field-programmable gate array. It contains (1) the hardware descriptions of the evolutionary design framework implemented in the programmable logic, (2) the software for both ARM processors of the Zynq platform and (3) the software required for generating the inputs and processing the outputs of the evolutionary design framework.The evolutionary design framework is based on our developed architecture where the candidate solutions can be established and mutated by fine-grained partial reconfiguration of look-up tables. Our advanced control unit and the reduced routing ensures that six candidate solutions can be evaluated in parallel (in a XC7Z020 device) and at a very high operational frequency (a larger device would allow to evaluate even more candidate solutions in parallel).The program code is deployed into one of the processors of Zynq-7000 and the evolutionary design framework into its programmable logic. Evolutionary on-line synthesis is performed by the other available processor. The functionality is transferred from software into hardware on-line, during runtime. This approach serves essentially the same purpose as high-level synthesis but the synthesis can be performed by a simple embedded computational platform and on-line.Version v1.0 of ZyEHW includes the complete implementation of the case study for image filter evolution (noise filtering and edge detection). (en)
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| Title
| - ZyEHW: Evolvable hardware in Xilinx Zynq-7000 field-programmable gate arrays
- ZyEHW: Evolvable hardware in Xilinx Zynq-7000 field-programmable gate arrays (en)
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| skos:prefLabel
| - ZyEHW: Evolvable hardware in Xilinx Zynq-7000 field-programmable gate arrays
- ZyEHW: Evolvable hardware in Xilinx Zynq-7000 field-programmable gate arrays (en)
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| skos:notation
| - RIV/00216305:26230/14:PR27655!RIV15-GA0-26230___
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| http://linked.open...avai/riv/aktivita
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| http://linked.open...avai/riv/aktivity
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| http://linked.open...vai/riv/dodaniDat
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| http://linked.open...aciTvurceVysledku
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| http://linked.open.../riv/druhVysledku
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| http://linked.open...iv/duvernostUdaju
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| http://linked.open...onomickeParametry
| - Volně šiřitelný software poskytovaný pod %22GNU General Public License, either version 3 or any later version%22.
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| http://linked.open...titaPredkladatele
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| http://linked.open...dnocenehoVysledku
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| http://linked.open...ai/riv/idVysledku
| - RIV/00216305:26230/14:PR27655
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| http://linked.open...terniIdentifikace
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| http://linked.open...riv/jazykVysledku
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| http://linked.open.../riv/klicovaSlova
| - Evolutionary design, field-programmable gate array, high-level synthesis, on-line synthesis, hardware architecture, image filters (en)
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| http://linked.open.../riv/klicoveSlovo
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| http://linked.open...ontrolniKodProRIV
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| http://linked.open...in/vavai/riv/obor
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| http://linked.open...ichTvurcuVysledku
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| http://linked.open...cetTvurcuVysledku
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| http://linked.open...vavai/riv/projekt
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| http://linked.open...UplatneniVysledku
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| http://linked.open...echnickeParametry
| - Volně šiřitelný software poskytovaný pod %22GNU General Public License, either version 3 or any later version%22.ZyEHW zahrnuje: 1. popis hardwaru (jazykem VHDL) implementovaný v programovatelné logice, 2. software (v jazyku C) pro obě ARM procesory dostupné na Zynq platformě a 3. software (v jazyku C) pro generovaní vstupů a zpracování výstupů evolučního návrhového systému. Systémové požadavky: - vývojová deska s Xilinx Zynq-7000, - Xilinx Vivado Design Suite pro syntézu hardwaru (stačí bezplatná licence), - gcc, make, ffmpeg, libxml2 a libtiff pro generovaní vstupů a zpracování výstupů evolučního návrhového systému.
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| http://linked.open...iv/tvurceVysledku
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| http://linked.open...avai/riv/vlastnik
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| http://linked.open...itiJinymSubjektem
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| http://localhost/t...ganizacniJednotka
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