About: An Abstraction of Multi-Port Memories with Arbitrary Addressable Units

Facets (new session)
Description
Metadata
Settings
- owl:sameAs
- Inference Rule:

About: An Abstraction of Multi-Port Memories with Arbitrary Addressable Units Goto Sponge NotDistinct Permalink

An Entity of Type : http://linked.opendata.cz/ontology/domain/vavai/Vysledek, within Data Space : linked.opendata.cz associated with source document(s)

Attributes	Values
rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	The paper describes a technique for automatic generation of abstract models of memories that can be used for efficient formal verification of hardware designs. Our approach is able to handle addressing of different sizes of data, such as quad words, double words, words, or bytes, at the same time. The technique is also applicable for memories with multiple read and write ports, memories with read and write operations with zero- or single-clock delay, and it allows the memory to start with a random initial state allowing one to formally verify the given design for all initial contents of the memory. Our abstraction allows large register-files and memories to be represented in a way that dramatically reduces the state space to be explored during formal verification of microprocessor designs. The paper describes a technique for automatic generation of abstract models of memories that can be used for efficient formal verification of hardware designs. Our approach is able to handle addressing of different sizes of data, such as quad words, double words, words, or bytes, at the same time. The technique is also applicable for memories with multiple read and write ports, memories with read and write operations with zero- or single-clock delay, and it allows the memory to start with a random initial state allowing one to formally verify the given design for all initial contents of the memory. Our abstraction allows large register-files and memories to be represented in a way that dramatically reduces the state space to be explored during formal verification of microprocessor designs. (en)
Title	An Abstraction of Multi-Port Memories with Arbitrary Addressable Units An Abstraction of Multi-Port Memories with Arbitrary Addressable Units (en)
skos:prefLabel	An Abstraction of Multi-Port Memories with Arbitrary Addressable Units An Abstraction of Multi-Port Memories with Arbitrary Addressable Units (en)
skos:notation	RIV/00216305:26230/13:PU106310!RIV14-MSM-26230___
http://linked.open...avai/predkladatel	Fakulta informačních technologií
http://linked.open...avai/riv/aktivita	S
http://linked.open...avai/riv/aktivity	S
http://linked.open...vai/riv/dodaniDat	2014
http://linked.open...aciTvurceVysledku	Vojnar, Tomáš Smrčka, Aleš Charvát, Lukáš
http://linked.open.../riv/druhVysledku	D - Článek ve sborníku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	Vysoké učení technické v Brně / Fakulta informačních technologií
http://linked.open...dnocenehoVysledku	60261
http://linked.open...ai/riv/idVysledku	RIV/00216305:26230/13:PU106310
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	memory, register file, automatic formal verification, model checking (en)
http://linked.open.../riv/klicoveSlovo	register file memory model checking automatic formal verification
http://linked.open...ontrolniKodProRIV	[F8ADAC0CD9E9]
http://linked.open...v/mistoKonaniAkce	Las Palmas de Gran Canaria
http://linked.open...i/riv/mistoVydani	Las Palmas de Grand Canaria
http://linked.open...i/riv/nazevZdroje	Proceedings of the 14th Computer Aided Systems Theory
http://linked.open...in/vavai/riv/obor	JC
http://linked.open...ichTvurcuVysledku	3 (xsd:int)
http://linked.open...cetTvurcuVysledku	3 (xsd:int)
http://linked.open...UplatneniVysledku	2013
http://linked.open...iv/tvurceVysledku	Vojnar, Tomáš Smrčka, Aleš Charvát, Lukáš
http://linked.open...vavai/riv/typAkce	WRD - Světová
http://linked.open.../riv/zahajeniAkce	2013-02-10 (xsd:date)
number of pages	2 (xsd:int)
http://purl.org/ne...btex#hasPublisher	The Universidad de Las Palmas de Gran Canaria
https://schema.org/isbn	978-84-695-6971-9
http://localhost/t...ganizacniJednotka	26230

Faceted Search & Find service v1.16.118 as of Jun 21 2024

Alternative Linked Data Documents: ODE Content Formats:

RDF

ODATA

Microdata

About

OpenLink Virtuoso version 07.20.3240 as of Jun 21 2024, on Linux (x86_64-pc-linux-gnu), Single-Server Edition (126 GB total memory, 36 GB memory in use)
Data on this page belongs to its respective rights holders.
Virtuoso Faceted Browser Copyright © 2009-2024 OpenLink Software