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  • Embedded systems often have to calculate some mathematical functions using iterative algorithms. When hard constraints are specified in terms of the area on the chip a possible solution is to implement the iterative algorithm by means of a microprogrammed digital circuit. In this paper, the first version of a new design framework is presented to automate the design and optimization of such microprogrammed systems. The framework utilizes evolutionary design and optimization techniques to find the most suitable implementation of the hardware architecture as well as the program for the programmable logic controller. The functionality of the proposed approach is evaluated using evolutionary design of three HW/SW systems under different constraints.
  • Embedded systems often have to calculate some mathematical functions using iterative algorithms. When hard constraints are specified in terms of the area on the chip a possible solution is to implement the iterative algorithm by means of a microprogrammed digital circuit. In this paper, the first version of a new design framework is presented to automate the design and optimization of such microprogrammed systems. The framework utilizes evolutionary design and optimization techniques to find the most suitable implementation of the hardware architecture as well as the program for the programmable logic controller. The functionality of the proposed approach is evaluated using evolutionary design of three HW/SW systems under different constraints. (en)
Title
  • Concurrent Evolution of Hardware and Software for Application-Specific Microprogrammed Systems
  • Concurrent Evolution of Hardware and Software for Application-Specific Microprogrammed Systems (en)
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  • Concurrent Evolution of Hardware and Software for Application-Specific Microprogrammed Systems
  • Concurrent Evolution of Hardware and Software for Application-Specific Microprogrammed Systems (en)
skos:notation
  • RIV/00216305:26230/13:PU106297!RIV14-GA0-26230___
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  • P(GAP103/10/1517), S
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  • 66679
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  • RIV/00216305:26230/13:PU106297
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  • evolvable hardware, codesign, LGP, microprogrammed architecture, microprogram (en)
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  • [6D9460D455AF]
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  • Singapore
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  • Singapur
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  • 2013 IEEE International Conference on Evolvable Systems (ICES)
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  • Sekanina, Lukáš
  • Minařík, Miloš
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number of pages
http://bibframe.org/vocab/doi
  • 10.1109/ICES.2013.6613281
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  • IEEE Computational Intelligence Society
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  • 978-1-4673-5869-9
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  • 26230
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