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  • This paper presents an evolvable hardware system, fully contained in an FPGA, which is capable of autonomously generating digital processing circuits, implemented on an array of processing elements (PEs). Candidate circuits are generated by an embedded evolutionary algorithm and implemented by means of dynamic partial reconfiguration, enabling evaluation in the final hardware. The PE array follows a systolic approach, and PEs do not contain extra logic such as path multiplexers or unused logic, so array performance is high. Hardware evaluation in the target device and the fast reconfiguration engine used yield smaller reconfiguration than evaluation times. This means that the complete evaluation cycle is faster than software-based approaches and previous evolvable digital systems. The selected application is digital image filtering and edge detection. The evolved filters yield better quality than classic linear and nonlinear filters using mean absolute error as standard comparison metric.
  • This paper presents an evolvable hardware system, fully contained in an FPGA, which is capable of autonomously generating digital processing circuits, implemented on an array of processing elements (PEs). Candidate circuits are generated by an embedded evolutionary algorithm and implemented by means of dynamic partial reconfiguration, enabling evaluation in the final hardware. The PE array follows a systolic approach, and PEs do not contain extra logic such as path multiplexers or unused logic, so array performance is high. Hardware evaluation in the target device and the fast reconfiguration engine used yield smaller reconfiguration than evaluation times. This means that the complete evaluation cycle is faster than software-based approaches and previous evolvable digital systems. The selected application is digital image filtering and edge detection. The evolved filters yield better quality than classic linear and nonlinear filters using mean absolute error as standard comparison metric. (en)
Title
  • Self-Reconfigurable Evolvable Hardware System for Adaptive Image Processing
  • Self-Reconfigurable Evolvable Hardware System for Adaptive Image Processing (en)
skos:prefLabel
  • Self-Reconfigurable Evolvable Hardware System for Adaptive Image Processing
  • Self-Reconfigurable Evolvable Hardware System for Adaptive Image Processing (en)
skos:notation
  • RIV/00216305:26230/13:PU106283!RIV14-GA0-26230___
http://linked.open...avai/predkladatel
http://linked.open...avai/riv/aktivita
http://linked.open...avai/riv/aktivity
  • P(ED1.1.00/02.0070), P(GAP103/10/1517)
http://linked.open...iv/cisloPeriodika
  • 8
http://linked.open...vai/riv/dodaniDat
http://linked.open...aciTvurceVysledku
http://linked.open.../riv/druhVysledku
http://linked.open...iv/duvernostUdaju
http://linked.open...titaPredkladatele
http://linked.open...dnocenehoVysledku
  • 104561
http://linked.open...ai/riv/idVysledku
  • RIV/00216305:26230/13:PU106283
http://linked.open...riv/jazykVysledku
http://linked.open.../riv/klicovaSlova
  • evolutionary computing, genetic algorithms, evolvable hardware, FPGAs, self-adaptive systems, reconfigurable hardware, adaptable architectures, autonomous systems (en)
http://linked.open.../riv/klicoveSlovo
http://linked.open...odStatuVydavatele
  • US - Spojené státy americké
http://linked.open...ontrolniKodProRIV
  • [E723D39221C4]
http://linked.open...i/riv/nazevZdroje
  • IEEE TRANSACTIONS ON COMPUTERS
http://linked.open...in/vavai/riv/obor
http://linked.open...ichTvurcuVysledku
http://linked.open...cetTvurcuVysledku
http://linked.open...vavai/riv/projekt
http://linked.open...UplatneniVysledku
http://linked.open...v/svazekPeriodika
  • 62
http://linked.open...iv/tvurceVysledku
  • De la Torre, Eduardo
  • Mora, Javier
  • Otero, Andres
  • Riesgo, Teresa
  • Salvador, Ruben
  • Sekanina, Lukáš
http://linked.open...ain/vavai/riv/wos
  • 000321221000002
issn
  • 0018-9340
number of pages
http://bibframe.org/vocab/doi
  • 10.1109/TC.2013.78
http://localhost/t...ganizacniJednotka
  • 26230
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