About: Test Platform for Fault Tolerant Systems Design Qualities Verification

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rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	In this paper, a methodology for fault tolerant systems design qualities verification is presented together with recovery technique for fault tolerant system after soft errors occurrence in SRAM-based FPGA. First, the principles of test platform based on external SEU injector are presented, all components of test platform and their role during SEU simulation are described. Then, the recovery technique based on the generic partial dynamic reconfiguration controller implemented inside FPGA is presented. The controller is used for the identification of faulty module in the fault tolerant system, reconfiguration of this module through ICAP interface and synchronization of the module after reconfiguration process with other modules in the system. The controller can be used for the identification of permanent faults in FPGA structure as well. The first experiments with test platform and reconfiguration controller are discussed in this paper. In this paper, a methodology for fault tolerant systems design qualities verification is presented together with recovery technique for fault tolerant system after soft errors occurrence in SRAM-based FPGA. First, the principles of test platform based on external SEU injector are presented, all components of test platform and their role during SEU simulation are described. Then, the recovery technique based on the generic partial dynamic reconfiguration controller implemented inside FPGA is presented. The controller is used for the identification of faulty module in the fault tolerant system, reconfiguration of this module through ICAP interface and synchronization of the module after reconfiguration process with other modules in the system. The controller can be used for the identification of permanent faults in FPGA structure as well. The first experiments with test platform and reconfiguration controller are discussed in this paper. (en)
Title	Test Platform for Fault Tolerant Systems Design Qualities Verification Test Platform for Fault Tolerant Systems Design Qualities Verification (en)
skos:prefLabel	Test Platform for Fault Tolerant Systems Design Qualities Verification Test Platform for Fault Tolerant Systems Design Qualities Verification (en)
skos:notation	RIV/00216305:26230/12:PU98180!RIV13-MSM-26230___
http://linked.open...avai/predkladatel	Fakulta informačních technologií
http://linked.open...avai/riv/aktivita	P Z
http://linked.open...avai/riv/aktivity	P(7H10013), P(ED1.1.00/02.0070), P(LD12036), Z(MSM0021630528)
http://linked.open...vai/riv/dodaniDat	2013
http://linked.open...aciTvurceVysledku	Straka, Martin Kotásek, Zdeněk Kaštil, Jan Mičulka, Lukáš
http://linked.open.../riv/druhVysledku	D - Článek ve sborníku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	Vysoké učení technické v Brně / Fakulta informačních technologií
http://linked.open...dnocenehoVysledku	173988
http://linked.open...ai/riv/idVysledku	RIV/00216305:26230/12:PU98180
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	controller, fault tolernat system, FPGA, SEU, injector, test platform (en)
http://linked.open.../riv/klicoveSlovo	fault tolernat system test platform SEU injector FPGA controller
http://linked.open...ontrolniKodProRIV	[4E2B1F1FE926]
http://linked.open...v/mistoKonaniAkce	Tallinn
http://linked.open...i/riv/mistoVydani	Tallin
http://linked.open...i/riv/nazevZdroje	15th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems
http://linked.open...in/vavai/riv/obor	IN
http://linked.open...ichTvurcuVysledku	4 (xsd:int)
http://linked.open...cetTvurcuVysledku	4 (xsd:int)
http://linked.open...vavai/riv/projekt	Methodologies for Fault Tolerant Systems Design Development, Implementation and Verification Reduced Certification Costs for Trusted Multi-core Platforms IT4Innovations Centre of Excellence
http://linked.open...UplatneniVysledku	2012
http://linked.open...iv/tvurceVysledku	Kaštil, Jan Kotásek, Zdeněk Straka, Martin Mičulka, Lukáš
http://linked.open...vavai/riv/typAkce	WRD - Světová
http://linked.open.../riv/zahajeniAkce	2012-04-18 (xsd:date)
http://linked.open...n/vavai/riv/zamer	Výzkum informačních technologií z hlediska bezpečnosti
number of pages	6 (xsd:int)
http://purl.org/ne...btex#hasPublisher	IEEE Computer Society
https://schema.org/isbn	978-1-4673-1185-4
http://localhost/t...ganizacniJednotka	26230
is http://linked.open...avai/riv/vysledek of	Test Platform for Fault Tolerant Systems Design Qualities Verification

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