About: Fault Tolerant System Design and SEU Injection based Testing

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An Entity of Type : http://linked.opendata.cz/ontology/domain/vavai/Vysledek, within Data Space : linked.opendata.cz associated with source document(s)

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rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	The methodology for design and testing of fault tolerant systems implemented into an FPGA platform with different types of diagnostic techniques is presented in this paper. Basic principles of partial dynamic reconfiguration are described together with their impact on the fault tolerance features of the digital design implemented into SRAM-based FPGA. The methodology includes detection and localization of a faulty module in the system and its repair and bringing the system back to the state in which it operates correctly. The automatic repair process of a faulty module is implemented by a partial dynamic reconfiguration driven by a generic controller inside FPGA. The presented methodology was verified on the ML506 development board with Virtex5 FPGA for different types of RTL components. Fault tolerant systems developed by the presented methodology were tested by means of the newly developed SEU simulation framework. The framework is based on the SEU simulation through the JTAG interface a The methodology for design and testing of fault tolerant systems implemented into an FPGA platform with different types of diagnostic techniques is presented in this paper. Basic principles of partial dynamic reconfiguration are described together with their impact on the fault tolerance features of the digital design implemented into SRAM-based FPGA. The methodology includes detection and localization of a faulty module in the system and its repair and bringing the system back to the state in which it operates correctly. The automatic repair process of a faulty module is implemented by a partial dynamic reconfiguration driven by a generic controller inside FPGA. The presented methodology was verified on the ML506 development board with Virtex5 FPGA for different types of RTL components. Fault tolerant systems developed by the presented methodology were tested by means of the newly developed SEU simulation framework. The framework is based on the SEU simulation through the JTAG interface a (en)
Title	Fault Tolerant System Design and SEU Injection based Testing Fault Tolerant System Design and SEU Injection based Testing (en)
skos:prefLabel	Fault Tolerant System Design and SEU Injection based Testing Fault Tolerant System Design and SEU Injection based Testing (en)
skos:notation	RIV/00216305:26230/12:PU98179!RIV13-GA0-26230___
http://linked.open...avai/predkladatel	Fakulta informačních technologií
http://linked.open...avai/riv/aktivita	P S Z
http://linked.open...avai/riv/aktivity	P(7H10013), P(GD102/09/H042), P(LD12036), S, Z(MSM0021630528)
http://linked.open...iv/cisloPeriodika	37
http://linked.open...vai/riv/dodaniDat	2013
http://linked.open...aciTvurceVysledku	Straka, Martin Kotásek, Zdeněk Kaštil, Jan Mičulka, Lukáš
http://linked.open.../riv/druhVysledku	J - Článek v odborném periodiku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	Vysoké učení technické v Brně / Fakulta informačních technologií
http://linked.open...dnocenehoVysledku	136260
http://linked.open...ai/riv/idVysledku	RIV/00216305:26230/12:PU98179
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	fault tolerant system, FPGA, partial reconfiguration, controller, on-line checker, duplex, TMR, SEU, simulation, framework, fault injection (en)
http://linked.open.../riv/klicoveSlovo	SEU FPGA framework simulation fault tolerant system TMR on-line checker duplex fault injection partial reconfiguration controller
http://linked.open...odStatuVydavatele	NL - Nizozemsko
http://linked.open...ontrolniKodProRIV	[D6D07C8D6FBE]
http://linked.open...i/riv/nazevZdroje	Microprocessors and Microsystems
http://linked.open...in/vavai/riv/obor	IN
http://linked.open...ichTvurcuVysledku	4 (xsd:int)
http://linked.open...cetTvurcuVysledku	4 (xsd:int)
http://linked.open...vavai/riv/projekt	Methodologies for Fault Tolerant Systems Design Development, Implementation and Verification Reduced Certification Costs for Trusted Multi-core Platforms Mathematical and Engineering Approaches to Developing Reliable and Secure Concurrent and Distributed Computer Systems
http://linked.open...UplatneniVysledku	2012
http://linked.open...v/svazekPeriodika	2013
http://linked.open...iv/tvurceVysledku	Kaštil, Jan Kotásek, Zdeněk Straka, Martin Mičulka, Lukáš
http://linked.open...n/vavai/riv/zamer	Výzkum informačních technologií z hlediska bezpečnosti
issn	0141-9331
number of pages	18 (xsd:int)
http://localhost/t...ganizacniJednotka	26230
is http://linked.open...avai/riv/vysledek of	Fault Tolerant System Design and SEU Injection based Testing

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