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  • We propose to utilize a formal verification algorithm to reduce the fitness evaluation time for evolutionary post-synthesis optimization in evolvable hardware. The proposed method assumes that a fully functional digital circuit is available. A post-synthesis optimization is then conducted using Cartesian Genetic Programming (CGP) which utilizes a satisfiability problem solver to decide whether a candidate solution is functionally correct or not. It is demonstrated that the method can optimize digital circuits of tens of inputs and thousands of gates. Furthermore, the number of gates was reduced for the LGSynth93 benchmark circuits by 37.8% on average with respect to results of the conventional SIS tool.
  • We propose to utilize a formal verification algorithm to reduce the fitness evaluation time for evolutionary post-synthesis optimization in evolvable hardware. The proposed method assumes that a fully functional digital circuit is available. A post-synthesis optimization is then conducted using Cartesian Genetic Programming (CGP) which utilizes a satisfiability problem solver to decide whether a candidate solution is functionally correct or not. It is demonstrated that the method can optimize digital circuits of tens of inputs and thousands of gates. Furthermore, the number of gates was reduced for the LGSynth93 benchmark circuits by 37.8% on average with respect to results of the conventional SIS tool. (en)
Title
  • Formal verification of candidate solutions for post-synthesis evolutionary optimization in evolvable hardware
  • Formal verification of candidate solutions for post-synthesis evolutionary optimization in evolvable hardware (en)
skos:prefLabel
  • Formal verification of candidate solutions for post-synthesis evolutionary optimization in evolvable hardware
  • Formal verification of candidate solutions for post-synthesis evolutionary optimization in evolvable hardware (en)
skos:notation
  • RIV/00216305:26230/11:PU96125!RIV12-MSM-26230___
http://linked.open...avai/predkladatel
http://linked.open...avai/riv/aktivita
http://linked.open...avai/riv/aktivity
  • P(GAP103/10/1517), P(GD102/09/H042), Z(MSM0021630528)
http://linked.open...iv/cisloPeriodika
  • 3
http://linked.open...vai/riv/dodaniDat
http://linked.open...aciTvurceVysledku
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http://linked.open...titaPredkladatele
http://linked.open...dnocenehoVysledku
  • 200133
http://linked.open...ai/riv/idVysledku
  • RIV/00216305:26230/11:PU96125
http://linked.open...riv/jazykVysledku
http://linked.open.../riv/klicovaSlova
  • genetic programming, circuit optimization, SAT solver, evolvable hardware (en)
http://linked.open.../riv/klicoveSlovo
http://linked.open...odStatuVydavatele
  • DE - Spolková republika Německo
http://linked.open...ontrolniKodProRIV
  • [023D21E0342F]
http://linked.open...i/riv/nazevZdroje
  • Genetic Programming and Evolvable Machines
http://linked.open...in/vavai/riv/obor
http://linked.open...ichTvurcuVysledku
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http://linked.open...vavai/riv/projekt
http://linked.open...UplatneniVysledku
http://linked.open...v/svazekPeriodika
  • 12
http://linked.open...iv/tvurceVysledku
  • Sekanina, Lukáš
  • Vašíček, Zdeněk
http://linked.open...n/vavai/riv/zamer
issn
  • 1389-2576
number of pages
http://localhost/t...ganizacniJednotka
  • 26230
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