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  • Assigning one (more) shared resource(s) to several requesters is a function of arbiters (allocators). This class of decision-making modules can be implemented in a number of ways, from hardware to firmware to software. The paper presents a new computer-aided technique that can produce representations of arbiters/allocators in a form of a Multi-Terminal Binary Decision Diagram (MTBDD) with close to minimum cost and width. This diagram can then serve as a prototype for a cascade of multiple-output look-up tables (LUTs) that implements the given function, or for efficient firmware implementation. The technique makes use of iterative decomposition of integer functions of Boolean variables and a variable-ordering heuristic to order variables. The LUT cascades lead directly to the pipelined design, simplify wiring and testing and can compete with the traditional FPGA design in performance and with PLA design in chip area.
  • Assigning one (more) shared resource(s) to several requesters is a function of arbiters (allocators). This class of decision-making modules can be implemented in a number of ways, from hardware to firmware to software. The paper presents a new computer-aided technique that can produce representations of arbiters/allocators in a form of a Multi-Terminal Binary Decision Diagram (MTBDD) with close to minimum cost and width. This diagram can then serve as a prototype for a cascade of multiple-output look-up tables (LUTs) that implements the given function, or for efficient firmware implementation. The technique makes use of iterative decomposition of integer functions of Boolean variables and a variable-ordering heuristic to order variables. The LUT cascades lead directly to the pipelined design, simplify wiring and testing and can compete with the traditional FPGA design in performance and with PLA design in chip area. (en)
Title
  • Design of Arbiters and Allocators Based on Multi-Terminal BDDs
  • Design of Arbiters and Allocators Based on Multi-Terminal BDDs (en)
skos:prefLabel
  • Design of Arbiters and Allocators Based on Multi-Terminal BDDs
  • Design of Arbiters and Allocators Based on Multi-Terminal BDDs (en)
skos:notation
  • RIV/00216305:26230/10:PU89625!RIV12-GA0-26230___
http://linked.open...avai/riv/aktivita
http://linked.open...avai/riv/aktivity
  • P(GA102/08/1429), P(GAP103/10/1517), P(GD102/09/H042), S, Z(MSM0021630528)
http://linked.open...iv/cisloPeriodika
  • 14
http://linked.open...vai/riv/dodaniDat
http://linked.open...aciTvurceVysledku
http://linked.open.../riv/druhVysledku
http://linked.open...iv/duvernostUdaju
http://linked.open...titaPredkladatele
http://linked.open...dnocenehoVysledku
  • 253524
http://linked.open...ai/riv/idVysledku
  • RIV/00216305:26230/10:PU89625
http://linked.open...riv/jazykVysledku
http://linked.open.../riv/klicovaSlova
  • Multi-Terminal BDDs, LUT cascades, iterative disjunctive decomposition, arbiter circuits, allocators. (en)
http://linked.open.../riv/klicoveSlovo
http://linked.open...odStatuVydavatele
  • AT - Rakouská republika
http://linked.open...ontrolniKodProRIV
  • [D747E427B108]
http://linked.open...i/riv/nazevZdroje
  • Journal of Universal Computer Science
http://linked.open...in/vavai/riv/obor
http://linked.open...ichTvurcuVysledku
http://linked.open...cetTvurcuVysledku
http://linked.open...vavai/riv/projekt
http://linked.open...UplatneniVysledku
http://linked.open...v/svazekPeriodika
  • 16
http://linked.open...iv/tvurceVysledku
  • Dvořák, Václav
  • Mikušek, Petr
http://linked.open...n/vavai/riv/zamer
issn
  • 0948-6968
number of pages
http://localhost/t...ganizacniJednotka
  • 26230
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