About: Hardware Accelerator for Evolutionary Image Filters Design

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An Entity of Type : http://linked.opendata.cz/ontology/domain/vavai/Vysledek, within Data Space : linked.opendata.cz associated with source document(s)

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rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	The EHWFILTER accelerator was developed in order to accelerate image filter evolution in hardware. It can automatically create a filter (e.g., to suppress shot noise) when noised image and uncorrupted original image are provided. The accelerator is implemented on the COMBO6X card equipped with Virtex II Pro 2VP50ff1517 FPGA. It consists of genetic unit, fitness unit and the so-called virtual reconfigurable circuit (VRC) which is utilized to evaluate candidate filters. Every image filter is considered as a digital circuit of nine 8-bit inputs and a single 8-bit output, which processes grayscale (8-bits/pixel) images. Training images are stored in external SRAM memories. The search algorithm is based on Cartesian Genetic Programming operating over 4x8 programmable elements, population size of 8 individuals, and 1 mutation/chromosome. This setting is default but can be changed. The accelerator is connected with PC using PCI bus. The system requires approx. 10 sec to produce a filter which is 44 The EHWFILTER accelerator was developed in order to accelerate image filter evolution in hardware. It can automatically create a filter (e.g., to suppress shot noise) when noised image and uncorrupted original image are provided. The accelerator is implemented on the COMBO6X card equipped with Virtex II Pro 2VP50ff1517 FPGA. It consists of genetic unit, fitness unit and the so-called virtual reconfigurable circuit (VRC) which is utilized to evaluate candidate filters. Every image filter is considered as a digital circuit of nine 8-bit inputs and a single 8-bit output, which processes grayscale (8-bits/pixel) images. Training images are stored in external SRAM memories. The search algorithm is based on Cartesian Genetic Programming operating over 4x8 programmable elements, population size of 8 individuals, and 1 mutation/chromosome. This setting is default but can be changed. The accelerator is connected with PC using PCI bus. The system requires approx. 10 sec to produce a filter which is 44 (en)
Title	Hardware Accelerator for Evolutionary Image Filters Design Hardware Accelerator for Evolutionary Image Filters Design (en)
skos:prefLabel	Hardware Accelerator for Evolutionary Image Filters Design Hardware Accelerator for Evolutionary Image Filters Design (en)
skos:notation	RIV/00216305:26230/09:PR24513!RIV10-MSM-26230___
http://linked.open...avai/riv/aktivita	P Z
http://linked.open...avai/riv/aktivity	P(GA102/07/0850), Z(MSM0021630528)
http://linked.open...vai/riv/dodaniDat	2010
http://linked.open...aciTvurceVysledku	Vašíček, Zdeněk Sekanina, Lukáš
http://linked.open.../riv/druhVysledku	G/B - Funkční vzorek
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...onomickeParametry	Cena závisí na počtu odebíraných kusů.
http://linked.open...titaPredkladatele	Vysoké učení technické v Brně / Fakulta informačních technologií
http://linked.open...dnocenehoVysledku	316850
http://linked.open...ai/riv/idVysledku	RIV/00216305:26230/09:PR24513
http://linked.open...terniIdentifikace	EHWFILTER
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open...vai/riv/kategorie	A - Do 5 mil. Kč
http://linked.open.../riv/klicovaSlova	accelerator, FPGA, Combo6X, evolutionary algorithm, image filter (en)
http://linked.open.../riv/klicoveSlovo	image filter FPGA evolutionary algorithm accelerator Combo6X
http://linked.open...ontrolniKodProRIV	[B6D3FB839E2C]
http://linked.open...okalizaceVysledku	Ústav počítačových systémů, Fakulta informačních technologií VUT v Brně, Božetěchova 2, 612 66 Brno, http://www.fit.vutbr.cz/units/UPSY/
http://linked.open...in/vavai/riv/obor	JC
http://linked.open...ichTvurcuVysledku	2 (xsd:int)
http://linked.open...cetTvurcuVysledku	2 (xsd:int)
http://linked.open...vavai/riv/projekt	Design and hardware implementation of a patent-invention machine
http://linked.open...UplatneniVysledku	2009
http://linked.open...echnickeParametry	Akcelerátor je implementován na kartě COMBO6X vybavené FPGA Virtex II Pro 2VP50ff1517 obsahující procesor PowerPC. Interně procesor pracuje na 300 MHz, podpůrná logika na 150 MHz. Ostatní komponenty akcelerátoru (virtuální rekonfigurovateln
http://linked.open...iv/tvurceVysledku	Sekanina, Lukáš Vašíček, Zdeněk
http://linked.open...avai/riv/vlastnik	Vysoké učení technické v Brně
http://linked.open...itiJinymSubjektem	N - Nabytí licence není nutné (výsledek není licencován)
http://linked.open...n/vavai/riv/zamer	Výzkum informačních technologií z hlediska bezpečnosti
http://localhost/t...ganizacniJednotka	26230
is http://linked.open...avai/riv/vysledek of	Hardware Accelerator for Evolutionary Image Filters Design Hardware Accelerator for Evolutionary Image Filters Design Hardware Accelerator for Evolutionary Image Filters Design Hardware Accelerator for Evolutionary Image Filters Design

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