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Description
| - Design of digital systems with a degree of regularity in physical placement of subsystems and in their interconnection has always been a much desired goal and is even more so at present. A regular logic has advantages which make it more attractive: short development time, better utilization of chip area, easy testability and easy modifications all end up in a lower cost. A one-dimensional cascade of look-up tables (LUT cells) is such a regular structure. LUTs are in fact multiple-input, multiple-output universal logic blocks. LUTs in block RAMs may provide support for reconfigurable architectures, asynchronous cascades or clocked pipelines; speed is competitive with other FPGA designs, layout and wiring are very easy. The LUT cascade is a promising reconfigurable logic device for future sub-100nm LSI technology. Sequential processing of LUT cascades by means of micro-engines with multi-way branching can improve firmware performance a great deal. In this presentation we will present a
- Design of digital systems with a degree of regularity in physical placement of subsystems and in their interconnection has always been a much desired goal and is even more so at present. A regular logic has advantages which make it more attractive: short development time, better utilization of chip area, easy testability and easy modifications all end up in a lower cost. A one-dimensional cascade of look-up tables (LUT cells) is such a regular structure. LUTs are in fact multiple-input, multiple-output universal logic blocks. LUTs in block RAMs may provide support for reconfigurable architectures, asynchronous cascades or clocked pipelines; speed is competitive with other FPGA designs, layout and wiring are very easy. The LUT cascade is a promising reconfigurable logic device for future sub-100nm LSI technology. Sequential processing of LUT cascades by means of micro-engines with multi-way branching can improve firmware performance a great deal. In this presentation we will present a (en)
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Title
| - On Lookup Table Cascade-Based Realizations of Arbiters
- On Lookup Table Cascade-Based Realizations of Arbiters (en)
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skos:prefLabel
| - On Lookup Table Cascade-Based Realizations of Arbiters
- On Lookup Table Cascade-Based Realizations of Arbiters (en)
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skos:notation
| - RIV/00216305:26230/08:PU78071!RIV12-GA0-26230___
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http://linked.open...avai/riv/aktivita
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http://linked.open...avai/riv/aktivity
| - P(GA102/07/0850), P(GA102/08/1429), Z(MSM0021630528)
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http://linked.open...vai/riv/dodaniDat
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http://linked.open...aciTvurceVysledku
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http://linked.open.../riv/druhVysledku
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http://linked.open...iv/duvernostUdaju
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http://linked.open...titaPredkladatele
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http://linked.open...dnocenehoVysledku
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http://linked.open...ai/riv/idVysledku
| - RIV/00216305:26230/08:PU78071
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http://linked.open...riv/jazykVysledku
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http://linked.open.../riv/klicovaSlova
| - LUT cascades, Multi-Terminal BDDs, iterative disjunctive decomposition, arbiter circuits (en)
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http://linked.open.../riv/klicoveSlovo
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http://linked.open...ontrolniKodProRIV
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http://linked.open...v/mistoKonaniAkce
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http://linked.open...i/riv/mistoVydani
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http://linked.open...i/riv/nazevZdroje
| - 4th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science
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http://linked.open...in/vavai/riv/obor
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http://linked.open...ichTvurcuVysledku
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http://linked.open...cetTvurcuVysledku
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http://linked.open...vavai/riv/projekt
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http://linked.open...UplatneniVysledku
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http://linked.open...iv/tvurceVysledku
| - Dvořák, Václav
- Mikušek, Petr
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http://linked.open...vavai/riv/typAkce
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http://linked.open.../riv/zahajeniAkce
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http://linked.open...n/vavai/riv/zamer
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number of pages
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http://purl.org/ne...btex#hasPublisher
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https://schema.org/isbn
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http://localhost/t...ganizacniJednotka
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is http://linked.open...avai/riv/vysledek
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