About: On Lookup Table Cascade-Based Realizations of Arbiters

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rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	Design of digital systems with a degree of regularity in physical placement of subsystems and in their interconnection has always been a much desired goal and is even more so at present. A regular logic has advantages which make it more attractive: short development time, better utilization of chip area, easy testability and easy modifications all end up in a lower cost. A one-dimensional cascade of look-up tables (LUT cells) is such a regular structure. LUTs are in fact multiple-input, multiple-output universal logic blocks. LUTs in block RAMs may provide support for reconfigurable architectures, asynchronous cascades or clocked pipelines; speed is competitive with other FPGA designs, layout and wiring are very easy. The LUT cascade is a promising reconfigurable logic device for future sub-100nm LSI technology. Sequential processing of LUT cascades by means of micro-engines with multi-way branching can improve firmware performance a great deal. In this presentation we will present a Design of digital systems with a degree of regularity in physical placement of subsystems and in their interconnection has always been a much desired goal and is even more so at present. A regular logic has advantages which make it more attractive: short development time, better utilization of chip area, easy testability and easy modifications all end up in a lower cost. A one-dimensional cascade of look-up tables (LUT cells) is such a regular structure. LUTs are in fact multiple-input, multiple-output universal logic blocks. LUTs in block RAMs may provide support for reconfigurable architectures, asynchronous cascades or clocked pipelines; speed is competitive with other FPGA designs, layout and wiring are very easy. The LUT cascade is a promising reconfigurable logic device for future sub-100nm LSI technology. Sequential processing of LUT cascades by means of micro-engines with multi-way branching can improve firmware performance a great deal. In this presentation we will present a (en)
Title	On Lookup Table Cascade-Based Realizations of Arbiters On Lookup Table Cascade-Based Realizations of Arbiters (en)
skos:prefLabel	On Lookup Table Cascade-Based Realizations of Arbiters On Lookup Table Cascade-Based Realizations of Arbiters (en)
skos:notation	RIV/00216305:26230/08:PU78071!RIV12-GA0-26230___
http://linked.open...avai/riv/aktivita	P Z
http://linked.open...avai/riv/aktivity	P(GA102/07/0850), P(GA102/08/1429), Z(MSM0021630528)
http://linked.open...vai/riv/dodaniDat	2012
http://linked.open...aciTvurceVysledku	Mikušek, Petr Dvořák, Václav
http://linked.open.../riv/druhVysledku	D - Článek ve sborníku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	Vysoké učení technické v Brně / Fakulta informačních technologií
http://linked.open...dnocenehoVysledku	384618
http://linked.open...ai/riv/idVysledku	RIV/00216305:26230/08:PU78071
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	LUT cascades, Multi-Terminal BDDs, iterative disjunctive decomposition, arbiter circuits (en)
http://linked.open.../riv/klicoveSlovo	LUT cascades Multi-Terminal BDDs arbiter circuits iterative disjunctive decomposition
http://linked.open...ontrolniKodProRIV	[285AB195FB00]
http://linked.open...v/mistoKonaniAkce	Znojmo
http://linked.open...i/riv/mistoVydani	Znojmo
http://linked.open...i/riv/nazevZdroje	4th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science
http://linked.open...in/vavai/riv/obor	JC
http://linked.open...ichTvurcuVysledku	2 (xsd:int)
http://linked.open...cetTvurcuVysledku	2 (xsd:int)
http://linked.open...vavai/riv/projekt	Safety and security of networked embedded system applications Design and hardware implementation of a patent-invention machine
http://linked.open...UplatneniVysledku	2008
http://linked.open...iv/tvurceVysledku	Dvořák, Václav Mikušek, Petr
http://linked.open...vavai/riv/typAkce	WRD - Světová
http://linked.open.../riv/zahajeniAkce	2008-11-14 (xsd:date)
http://linked.open...n/vavai/riv/zamer	Výzkum informačních technologií z hlediska bezpečnosti
number of pages	1 (xsd:int)
http://purl.org/ne...btex#hasPublisher	Masaryk University
https://schema.org/isbn	978-80-7355-082-0
http://localhost/t...ganizacniJednotka	26230
is http://linked.open...avai/riv/vysledek of	On Lookup Table Cascade-Based Realizations of Arbiters On Lookup Table Cascade-Based Realizations of Arbiters

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