About: Evolution of Synthetic RTL Benchmark Circuits with Predefined Testability

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Description	This article presents a new real-world application of evolutionary computing in the area of digital-circuits testing. A method is described which enables to evolve large synthetic RTL benchmark circuits with a predefined structure and testability. Using the proposed method, a new collection of synthetic benchmark circuits was developed. These benchmark circuits will be useful in a validation process of novel algorithms and tools in the area of digital-circuits testing. Evolved benchmark circuits currently represent the most complex benchmark circuits with a known level of testability. Furthermore, these circuits are the largest that have ever been designed by means of evolutionary algorithms. This work also investigates suitable parameters of the evolutionary algorithm for this problem and explores the limits in the complexity of evolved circuits. This article presents a new real-world application of evolutionary computing in the area of digital-circuits testing. A method is described which enables to evolve large synthetic RTL benchmark circuits with a predefined structure and testability. Using the proposed method, a new collection of synthetic benchmark circuits was developed. These benchmark circuits will be useful in a validation process of novel algorithms and tools in the area of digital-circuits testing. Evolved benchmark circuits currently represent the most complex benchmark circuits with a known level of testability. Furthermore, these circuits are the largest that have ever been designed by means of evolutionary algorithms. This work also investigates suitable parameters of the evolutionary algorithm for this problem and explores the limits in the complexity of evolved circuits. (en)
Title	Evolution of Synthetic RTL Benchmark Circuits with Predefined Testability Evolution of Synthetic RTL Benchmark Circuits with Predefined Testability (en)
skos:prefLabel	Evolution of Synthetic RTL Benchmark Circuits with Predefined Testability Evolution of Synthetic RTL Benchmark Circuits with Predefined Testability (en)
skos:notation	RIV/00216305:26230/08:PU76736!RIV10-MSM-26230___
http://linked.open...avai/riv/aktivita	P Z
http://linked.open...avai/riv/aktivity	P(GA102/07/0850), P(GD102/05/H050), Z(MSM0021630528)
http://linked.open...iv/cisloPeriodika	3
http://linked.open...vai/riv/dodaniDat	2010
http://linked.open...aciTvurceVysledku	Sekanina, Lukáš Kotásek, Zdeněk Pečenka, Tomáš
http://linked.open.../riv/druhVysledku	J - Článek v odborném periodiku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	Vysoké učení technické v Brně / Fakulta informačních technologií
http://linked.open...dnocenehoVysledku	366942
http://linked.open...ai/riv/idVysledku	RIV/00216305:26230/08:PU76736
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	evolutionary algorithm, digital circuit, testability analysis (en)
http://linked.open.../riv/klicoveSlovo	digital circuit evolutionary algorithm testability analysis
http://linked.open...odStatuVydavatele	US - Spojené státy americké
http://linked.open...ontrolniKodProRIV	[EE4A6F307651]
http://linked.open...i/riv/nazevZdroje	ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS
http://linked.open...in/vavai/riv/obor	JC
http://linked.open...ichTvurcuVysledku	3 (xsd:int)
http://linked.open...cetTvurcuVysledku	3 (xsd:int)
http://linked.open...vavai/riv/projekt	Design and hardware implementation of a patent-invention machine Integrated Approach to Education of PhD Students in the Area of Parallel and Distributed Systems
http://linked.open...UplatneniVysledku	2008
http://linked.open...v/svazekPeriodika	13
http://linked.open...iv/tvurceVysledku	Kotásek, Zdeněk Sekanina, Lukáš Pečenka, Tomáš
http://linked.open...n/vavai/riv/zamer	Výzkum informačních technologií z hlediska bezpečnosti
issn	1084-4309
number of pages	21 (xsd:int)
http://localhost/t...ganizacniJednotka	26230
is http://linked.open...avai/riv/vysledek of	Evolution of Synthetic RTL Benchmark Circuits with Predefined Testability Evolution of Synthetic RTL Benchmark Circuits with Predefined Testability Evolution of Synthetic RTL Benchmark Circuits with Predefined Testability Evolution of Synthetic RTL Benchmark Circuits with Predefined Testability

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