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  • This paper presents a new algorithm of iterative decomposition for multiple-output Boolean functions with an embedded heuristics to order variables. The algorithm produces a cascade of look-up tables (LUTs) that implements the given function and simultaneously a sub-optimal Multi-Terminal Binary Decision Diagram (MTBDD). The LUT cascade can be used for pipelined processing on FPGAs with BRAMs or at a non-traditional synthesis of large combinational and sequential circuits. On the other hand, suboptimal MTBBDs can serve as prototypes for efficient firmware implementation, especially when a micro-programmed controller that firmware runs on supports multi-way branching. A novel technique is illustrated on practical examples of three types of arbiters. It may be quite useful as a more flexible alternative implementation of digital systems with increased testability and improved manufacturability.
  • This paper presents a new algorithm of iterative decomposition for multiple-output Boolean functions with an embedded heuristics to order variables. The algorithm produces a cascade of look-up tables (LUTs) that implements the given function and simultaneously a sub-optimal Multi-Terminal Binary Decision Diagram (MTBDD). The LUT cascade can be used for pipelined processing on FPGAs with BRAMs or at a non-traditional synthesis of large combinational and sequential circuits. On the other hand, suboptimal MTBBDs can serve as prototypes for efficient firmware implementation, especially when a micro-programmed controller that firmware runs on supports multi-way branching. A novel technique is illustrated on practical examples of three types of arbiters. It may be quite useful as a more flexible alternative implementation of digital systems with increased testability and improved manufacturability. (en)
Title
  • On Lookup Table Cascade-Based Realizations of Arbiters
  • On Lookup Table Cascade-Based Realizations of Arbiters (en)
skos:prefLabel
  • On Lookup Table Cascade-Based Realizations of Arbiters
  • On Lookup Table Cascade-Based Realizations of Arbiters (en)
skos:notation
  • RIV/00216305:26230/08:PU76721!RIV12-GA0-26230___
http://linked.open...avai/riv/aktivita
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  • P(GA102/07/0850), P(GA102/08/1429), Z(MSM0021630528)
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  • 384619
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  • RIV/00216305:26230/08:PU76721
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  • LUT cascades, Multi-Terminal BDDs, iterative disjunctive decomposition, arbiter circuits (en)
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http://linked.open...ontrolniKodProRIV
  • [14F8364D1000]
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  • Parma
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  • Parma
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  • 11th EUROMICRO Conference on Digital System Design DSD 2008
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  • Dvořák, Václav
  • Mikušek, Petr
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http://linked.open...n/vavai/riv/zamer
number of pages
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  • IEEE Computer Society
https://schema.org/isbn
  • 978-0-7695-3277-6
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  • 26230
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