About: Evolutionary Functional Recovery in Virtual Reconfigurable Circuits     Goto   Sponge   NotDistinct   Permalink

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Description
  • A virtual reconfigurable circuit (VRC) is a domain-specific reconfigurable device developed using an ordinary FPGA in order to easily implement evolvable hardware applications. While a fast partial run-time reconfiguration and application-specific programmable elements represent the main advantages of VRC, the main disadvantage of the VRC is the area consumed. This study describes experiments conducted to estimate how the use of VRC influences the dependability of FPGA-based evolvable systems. It is shown that these systems are not as sensitive to faults as their area-demanding implementations might suggest. An evolutionary algorithm is utilized to design fault tolerant circuits as well as to perform an automatic functional recovery when faults are detected in the configuration memory of the FPGA. All the experiments are performed on models of reconfigurable devices. 
  • A virtual reconfigurable circuit (VRC) is a domain-specific reconfigurable device developed using an ordinary FPGA in order to easily implement evolvable hardware applications. While a fast partial run-time reconfiguration and application-specific programmable elements represent the main advantages of VRC, the main disadvantage of the VRC is the area consumed. This study describes experiments conducted to estimate how the use of VRC influences the dependability of FPGA-based evolvable systems. It is shown that these systems are not as sensitive to faults as their area-demanding implementations might suggest. An evolutionary algorithm is utilized to design fault tolerant circuits as well as to perform an automatic functional recovery when faults are detected in the configuration memory of the FPGA. All the experiments are performed on models of reconfigurable devices.  (en)
  • Virtuální rekonfigurovatelný obvod (VRC) je speciální rekonfigurovatelné zařízení vytvořené v běžném obvodě typu FPGA s cílem usnadnit implementaci vyvíjejících se obvodů. Zatímco rychlá parciální rekonfigurace a aplikačně specifické výpočetní elementy jsou výhodou VRC, jejich největší nevýhodou je velké množství zdrojů nutných k implementaci v FPGA. Tato studie ukazuje, jak použití VRC ovlivňuje spolehlivost vyvíjejících se systémů v FPGA. Ukazuje se, že tyto vyvíjející se systémy nejsou až tak náchylné k poruchám, jak by jejich vysoká implementační cena mohla evokovat. Evoluční algoritmus je použit pro návrh odolných obvodů a k obnovení činnosti obvodu při poruše. Všechny experimenty byly provedeny na modelech rekonfigurovatelných zařízení. (cs)
Title
  • Evolutionary Functional Recovery in Virtual Reconfigurable Circuits
  • Evolutionary Functional Recovery in Virtual Reconfigurable Circuits (en)
  • Evolutionary Functional Recovery in Virtual Reconfigurable Circuits (cs)
skos:prefLabel
  • Evolutionary Functional Recovery in Virtual Reconfigurable Circuits
  • Evolutionary Functional Recovery in Virtual Reconfigurable Circuits (en)
  • Evolutionary Functional Recovery in Virtual Reconfigurable Circuits (cs)
skos:notation
  • RIV/00216305:26230/07:PU70825!RIV08-MSM-26230___
http://linked.open.../vavai/riv/strany
  • 1-22
http://linked.open...avai/riv/aktivita
http://linked.open...avai/riv/aktivity
  • P(GA102/06/0599), Z(MSM0021630528)
http://linked.open...iv/cisloPeriodika
  • 2
http://linked.open...vai/riv/dodaniDat
http://linked.open...aciTvurceVysledku
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http://linked.open...iv/duvernostUdaju
http://linked.open...titaPredkladatele
http://linked.open...dnocenehoVysledku
  • 420890
http://linked.open...ai/riv/idVysledku
  • RIV/00216305:26230/07:PU70825
http://linked.open...riv/jazykVysledku
http://linked.open.../riv/klicovaSlova
  • hardware, logic design, reliability, reconfigurable circuit, evolutionary algorithm (en)
http://linked.open.../riv/klicoveSlovo
http://linked.open...odStatuVydavatele
  • US - Spojené státy americké
http://linked.open...ontrolniKodProRIV
  • [CCA566284C7F]
http://linked.open...i/riv/nazevZdroje
  • ACM Journal on Emerging Technologies in Computing Systems
http://linked.open...in/vavai/riv/obor
http://linked.open...ichTvurcuVysledku
http://linked.open...cetTvurcuVysledku
http://linked.open...vavai/riv/projekt
http://linked.open...UplatneniVysledku
http://linked.open...v/svazekPeriodika
  • 3
http://linked.open...iv/tvurceVysledku
  • Sekanina, Lukáš
http://linked.open...n/vavai/riv/zamer
issn
  • 1550-4832
number of pages
http://localhost/t...ganizacniJednotka
  • 26230
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