About: Online Protocol Testing for FPGA Based Fault Tolerant Systems

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An Entity of Type : http://linked.opendata.cz/ontology/domain/vavai/Vysledek, within Data Space : linked.opendata.cz associated with source document(s)

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rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	In this paper, the methodology for automated design of checker for<br>communication protocol testing is presented. Based on the level of<br>checking, different design strategies can be performed - in the<br>paper the lowest level is presented. The definition of dedicated<br>language for the description of possible communication faults is<br>presented. The core generator is used to produce VHDL code<br>describing the behaviour of the checker. In this paper, the methodology for automated design of checker for<br>communication protocol testing is presented. Based on the level of<br>checking, different design strategies can be performed - in the<br>paper the lowest level is presented. The definition of dedicated<br>language for the description of possible communication faults is<br>presented. The core generator is used to produce VHDL code<br>describing the behaviour of the checker. (en) In this paper, the methodology for automated design of checker for<br>communication protocol testing is presented. Based on the level of<br>checking, different design strategies can be performed - in the<br>paper the lowest level is presented. The definition of dedicated<br>language for the description of possible communication faults is<br>presented. The core generator is used to produce VHDL code<br>describing the behaviour of the checker. (cs)
Title	Online Protocol Testing for FPGA Based Fault Tolerant Systems Online Protocol Testing for FPGA Based Fault Tolerant Systems (en) Online Protocol Testing for FPGA Based Fault Tolerant Systems (cs)
skos:prefLabel	Online Protocol Testing for FPGA Based Fault Tolerant Systems Online Protocol Testing for FPGA Based Fault Tolerant Systems (en) Online Protocol Testing for FPGA Based Fault Tolerant Systems (cs)
skos:notation	RIV/00216305:26230/07:PU70806!RIV08-MSM-26230___
http://linked.open.../vavai/riv/strany	676-679
http://linked.open...avai/riv/aktivita	P Z
http://linked.open...avai/riv/aktivity	P(GD102/05/H050), Z(MSM0021630528)
http://linked.open...vai/riv/dodaniDat	2008
http://linked.open...aciTvurceVysledku	Tobola, Jiří Kořenek, Jan Straka, Martin Martínek, Tomáš Kotásek, Zdeněk
http://linked.open.../riv/druhVysledku	D - Článek ve sborníku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	Vysoké učení technické v Brně / Fakulta informačních technologií
http://linked.open...dnocenehoVysledku	439526
http://linked.open...ai/riv/idVysledku	RIV/00216305:26230/07:PU70806
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	Communication Protocol Testing, Fault Tolerant Systems, Checker, FPGA, VHDL (en)
http://linked.open.../riv/klicoveSlovo	VHDL Checker FPGA Communication Protocol Testing Fault Tolerant Systems
http://linked.open...ontrolniKodProRIV	[11E1045FA648]
http://linked.open...v/mistoKonaniAkce	Lübeck
http://linked.open...i/riv/mistoVydani	Lubeck, Germany
http://linked.open...i/riv/nazevZdroje	10th EUROMICRO Conference on Digital System Design DSD 2007
http://linked.open...in/vavai/riv/obor	JC
http://linked.open...ichTvurcuVysledku	5 (xsd:int)
http://linked.open...cetTvurcuVysledku	5 (xsd:int)
http://linked.open...vavai/riv/projekt	Integrated Approach to Education of PhD Students in the Area of Parallel and Distributed Systems
http://linked.open...UplatneniVysledku	2007
http://linked.open...iv/tvurceVysledku	Kotásek, Zdeněk Martínek, Tomáš Straka, Martin Kořenek, Jan Tobola, Jiří
http://linked.open...vavai/riv/typAkce	WRD - Světová
http://linked.open.../riv/zahajeniAkce	2007-08-27 (xsd:date)
http://linked.open...n/vavai/riv/zamer	Výzkum informačních technologií z hlediska bezpečnosti
number of pages	4 (xsd:int)
http://purl.org/ne...btex#hasPublisher	IEEE Computer Society
https://schema.org/isbn	0-7695-2978-X
http://localhost/t...ganizacniJednotka	26230
is http://linked.open...avai/riv/vysledek of	Online Protocol Testing for FPGA Based Fault Tolerant Systems Online Protocol Testing for FPGA Based Fault Tolerant Systems Online Protocol Testing for FPGA Based Fault Tolerant Systems

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