Attributes | Values |
---|
rdf:type
| |
Description
| - In this paper, a new circuit architecture for image filter evolution is proposed. The evolvable system is based on the implementation of a search algorithm in the PowerPC processor which is available in Xilinx Virtex II Pro FPGAs. Candidate filters are evaluated in a domain-specific virtual reconfigurable circuit implemented using a reconfigurable logic of the same FPGA. As the PowerPC processor enables to execute more sophisticated search algorithms than an original solely circuit-based solution, a higher performance can be obtained. In the FPGA, a resulting human-competitive filter can be evolved in 15 seconds in average.
- In this paper, a new circuit architecture for image filter evolution is proposed. The evolvable system is based on the implementation of a search algorithm in the PowerPC processor which is available in Xilinx Virtex II Pro FPGAs. Candidate filters are evaluated in a domain-specific virtual reconfigurable circuit implemented using a reconfigurable logic of the same FPGA. As the PowerPC processor enables to execute more sophisticated search algorithms than an original solely circuit-based solution, a higher performance can be obtained. In the FPGA, a resulting human-competitive filter can be evolved in 15 seconds in average. (en)
- In this paper, a new circuit architecture for image filter evolution is proposed. The evolvable system is based on the implementation of a search algorithm in the PowerPC processor which is available in Xilinx Virtex II Pro FPGAs. Candidate filters are evaluated in a domain-specific virtual reconfigurable circuit implemented using a reconfigurable logic of the same FPGA. As the PowerPC processor enables to execute more sophisticated search algorithms than an original solely circuit-based solution, a higher performance can be obtained. In the FPGA, a resulting human-competitive filter can be evolved in 15 seconds in average. (cs)
|
Title
| - An Evolvable Hardware System in Xilinx Virtex II Pro FPGA
- An Evolvable Hardware System in Xilinx Virtex II Pro FPGA (en)
- An Evolvable Hardware System in Xilinx Virtex II Pro FPGA (cs)
|
skos:prefLabel
| - An Evolvable Hardware System in Xilinx Virtex II Pro FPGA
- An Evolvable Hardware System in Xilinx Virtex II Pro FPGA (en)
- An Evolvable Hardware System in Xilinx Virtex II Pro FPGA (cs)
|
skos:notation
| - RIV/00216305:26230/07:PU70783!RIV08-MSM-26230___
|
http://linked.open.../vavai/riv/strany
| |
http://linked.open...avai/riv/aktivita
| |
http://linked.open...avai/riv/aktivity
| - P(GA102/07/0850), Z(MSM0021630528)
|
http://linked.open...iv/cisloPeriodika
| |
http://linked.open...vai/riv/dodaniDat
| |
http://linked.open...aciTvurceVysledku
| |
http://linked.open.../riv/druhVysledku
| |
http://linked.open...iv/duvernostUdaju
| |
http://linked.open...titaPredkladatele
| |
http://linked.open...dnocenehoVysledku
| |
http://linked.open...ai/riv/idVysledku
| - RIV/00216305:26230/07:PU70783
|
http://linked.open...riv/jazykVysledku
| |
http://linked.open.../riv/klicovaSlova
| - image filter, evolvable hardware, FPGA (en)
|
http://linked.open.../riv/klicoveSlovo
| |
http://linked.open...odStatuVydavatele
| - CH - Švýcarská konfederace
|
http://linked.open...ontrolniKodProRIV
| |
http://linked.open...i/riv/nazevZdroje
| - International Journal of Innovative Computing and Applications
|
http://linked.open...in/vavai/riv/obor
| |
http://linked.open...ichTvurcuVysledku
| |
http://linked.open...cetTvurcuVysledku
| |
http://linked.open...vavai/riv/projekt
| |
http://linked.open...UplatneniVysledku
| |
http://linked.open...v/svazekPeriodika
| |
http://linked.open...iv/tvurceVysledku
| - Sekanina, Lukáš
- Vašíček, Zdeněk
|
http://linked.open...n/vavai/riv/zamer
| |
issn
| |
number of pages
| |
http://localhost/t...ganizacniJednotka
| |
is http://linked.open...avai/riv/vysledek
of | |