About: An Evolvable Hardware System in Xilinx Virtex II Pro FPGA

Facets (new session)
Description
Metadata
Settings
- owl:sameAs
- Inference Rule:

About: An Evolvable Hardware System in Xilinx Virtex II Pro FPGA Goto Sponge NotDistinct Permalink

An Entity of Type : http://linked.opendata.cz/ontology/domain/vavai/Vysledek, within Data Space : linked.opendata.cz associated with source document(s)

Attributes	Values
rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	In this paper, a new circuit architecture for image filter evolution is proposed. The evolvable system is based on the implementation of a search algorithm in the PowerPC processor which is available in Xilinx Virtex II Pro FPGAs. Candidate filters are evaluated in a domain-specific virtual reconfigurable circuit implemented using a reconfigurable logic of the same FPGA. As the PowerPC processor enables to execute more sophisticated search algorithms than an original solely circuit-based solution, a higher performance can be obtained. In the FPGA, a resulting human-competitive filter can be evolved in 15 seconds in average.   In this paper, a new circuit architecture for image filter evolution is proposed. The evolvable system is based on the implementation of a search algorithm in the PowerPC processor which is available in Xilinx Virtex II Pro FPGAs. Candidate filters are evaluated in a domain-specific virtual reconfigurable circuit implemented using a reconfigurable logic of the same FPGA. As the PowerPC processor enables to execute more sophisticated search algorithms than an original solely circuit-based solution, a higher performance can be obtained. In the FPGA, a resulting human-competitive filter can be evolved in 15 seconds in average.   (en) In this paper, a new circuit architecture for image filter evolution is proposed. The evolvable system is based on the implementation of a search algorithm in the PowerPC processor which is available in Xilinx Virtex II Pro FPGAs. Candidate filters are evaluated in a domain-specific virtual reconfigurable circuit implemented using a reconfigurable logic of the same FPGA. As the PowerPC processor enables to execute more sophisticated search algorithms than an original solely circuit-based solution, a higher performance can be obtained. In the FPGA, a resulting human-competitive filter can be evolved in 15 seconds in average.   (cs)
Title	An Evolvable Hardware System in Xilinx Virtex II Pro FPGA An Evolvable Hardware System in Xilinx Virtex II Pro FPGA (en) An Evolvable Hardware System in Xilinx Virtex II Pro FPGA (cs)
skos:prefLabel	An Evolvable Hardware System in Xilinx Virtex II Pro FPGA An Evolvable Hardware System in Xilinx Virtex II Pro FPGA (en) An Evolvable Hardware System in Xilinx Virtex II Pro FPGA (cs)
skos:notation	RIV/00216305:26230/07:PU70783!RIV08-MSM-26230___
http://linked.open.../vavai/riv/strany	63-73
http://linked.open...avai/riv/aktivita	P Z
http://linked.open...avai/riv/aktivity	P(GA102/07/0850), Z(MSM0021630528)
http://linked.open...iv/cisloPeriodika	1
http://linked.open...vai/riv/dodaniDat	2008
http://linked.open...aciTvurceVysledku	Vašíček, Zdeněk Sekanina, Lukáš
http://linked.open.../riv/druhVysledku	J - Článek v odborném periodiku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	Vysoké učení technické v Brně / Fakulta informačních technologií
http://linked.open...dnocenehoVysledku	409313
http://linked.open...ai/riv/idVysledku	RIV/00216305:26230/07:PU70783
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	image filter, evolvable hardware, FPGA (en)
http://linked.open.../riv/klicoveSlovo	image filter FPGA evolvable hardware
http://linked.open...odStatuVydavatele	CH - Švýcarská konfederace
http://linked.open...ontrolniKodProRIV	[60F88F3A6221]
http://linked.open...i/riv/nazevZdroje	International Journal of Innovative Computing and Applications
http://linked.open...in/vavai/riv/obor	JC
http://linked.open...ichTvurcuVysledku	2 (xsd:int)
http://linked.open...cetTvurcuVysledku	2 (xsd:int)
http://linked.open...vavai/riv/projekt	Design and hardware implementation of a patent-invention machine
http://linked.open...UplatneniVysledku	2007
http://linked.open...v/svazekPeriodika	1
http://linked.open...iv/tvurceVysledku	Sekanina, Lukáš Vašíček, Zdeněk
http://linked.open...n/vavai/riv/zamer	Výzkum informačních technologií z hlediska bezpečnosti
issn	1751-648X
number of pages	11 (xsd:int)
http://localhost/t...ganizacniJednotka	26230
is http://linked.open...avai/riv/vysledek of	An Evolvable Hardware System in Xilinx Virtex II Pro FPGA An Evolvable Hardware System in Xilinx Virtex II Pro FPGA An Evolvable Hardware System in Xilinx Virtex II Pro FPGA

Faceted Search & Find service v1.16.118 as of Jun 21 2024

Alternative Linked Data Documents: ODE Content Formats:

RDF

ODATA

Microdata

About

OpenLink Virtuoso version 07.20.3240 as of Jun 21 2024, on Linux (x86_64-pc-linux-gnu), Single-Server Edition (126 GB total memory, 85 GB memory in use)
Data on this page belongs to its respective rights holders.
Virtuoso Faceted Browser Copyright © 2009-2024 OpenLink Software