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| - <!-- @page { size: 21cm 29.7cm; margin: 2cm } P { margin-bottom: 0.21cm } --> <p>The paper gives a brief view on possibilities how to exploit modeling features of Simulink interconnected with Processor Expert to finalize code of VHDL components placed in FPGA. Such an FPGA can be used to deliver powerful co-processing unit where main processing unit (e.g. microcontroller) is not powerful enough and/or the task to be solved is somehow special.
- <!-- @page { size: 21cm 29.7cm; margin: 2cm } P { margin-bottom: 0.21cm } --> <p>The paper gives a brief view on possibilities how to exploit modeling features of Simulink interconnected with Processor Expert to finalize code of VHDL components placed in FPGA. Such an FPGA can be used to deliver powerful co-processing unit where main processing unit (e.g. microcontroller) is not powerful enough and/or the task to be solved is somehow special. (en)
- Tento článek stručně popisuje možnosti, jak spojit modelovací vlastnosti prostředí Simulink propojeného s programem Processor Expert pro simulování a generování kódu VHDL komponent umístěných v FPGA čipu. Tyto komponenty mohou být použity jako aplikačně specifické akcelerátory, kde hlavní výpočetní jednotka (např. mikrokontrolér) není dostatečně výkonný.<br> (cs)
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Title
| - FPGA Components in Simulink
- FPGA Components in Simulink (en)
- FPGA komponenty v prostředí Simulinku (cs)
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skos:prefLabel
| - FPGA Components in Simulink
- FPGA Components in Simulink (en)
- FPGA komponenty v prostředí Simulinku (cs)
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skos:notation
| - RIV/00216305:26230/06:PU66965!RIV07-GA0-26230___
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http://linked.open.../vavai/riv/strany
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http://linked.open...avai/riv/aktivita
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http://linked.open...avai/riv/aktivity
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http://linked.open...vai/riv/dodaniDat
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http://linked.open...aciTvurceVysledku
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http://linked.open.../riv/druhVysledku
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http://linked.open...iv/duvernostUdaju
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http://linked.open...titaPredkladatele
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http://linked.open...dnocenehoVysledku
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http://linked.open...ai/riv/idVysledku
| - RIV/00216305:26230/06:PU66965
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http://linked.open...riv/jazykVysledku
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http://linked.open.../riv/klicovaSlova
| - <,!-- @page { size: 21cm 29.7cm, margin: 2cm } P { margin-bottom: 0.21cm } -->, <p>VHDL, FPGA, code generation, Simulink, modeling, Processor Expert (en)
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http://linked.open.../riv/klicoveSlovo
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http://linked.open...ontrolniKodProRIV
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http://linked.open...v/mistoKonaniAkce
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http://linked.open...i/riv/mistoVydani
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http://linked.open...i/riv/nazevZdroje
| - Proceedings of XXVIIIth International Autumn Colloquium ASIS 2006
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http://linked.open...in/vavai/riv/obor
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http://linked.open...ichTvurcuVysledku
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http://linked.open...cetTvurcuVysledku
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http://linked.open...vavai/riv/projekt
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http://linked.open...UplatneniVysledku
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http://linked.open...iv/tvurceVysledku
| - Kotásek, Zdeněk
- Martínek, Tomáš
- Kořenek, Jan
- Černý, Stanislav
- Stružka, Petr
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http://linked.open...vavai/riv/typAkce
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http://linked.open.../riv/zahajeniAkce
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number of pages
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http://purl.org/ne...btex#hasPublisher
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https://schema.org/isbn
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http://localhost/t...ganizacniJednotka
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is http://linked.open...avai/riv/vysledek
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