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  • Polymorphic gates exhibit one or more additional functions in addition to the main function of the gate. The additional functions can be activated under certain conditions by changing control parameters (such as temperature, Vdd, light etc.) of the circuit. This paper shows a non-trivial polymorphic combinational circuit (5 bit majority/Boolean symmetry) which was designed at the gate level and then simulated using polymorphic NAND/NOR gates controlled by Vdd and some conventional gates at the transistor level. PSpice simulations have shown correct behavior of this circuit.<br>
  • Polymorphic gates exhibit one or more additional functions in addition to the main function of the gate. The additional functions can be activated under certain conditions by changing control parameters (such as temperature, Vdd, light etc.) of the circuit. This paper shows a non-trivial polymorphic combinational circuit (5 bit majority/Boolean symmetry) which was designed at the gate level and then simulated using polymorphic NAND/NOR gates controlled by Vdd and some conventional gates at the transistor level. PSpice simulations have shown correct behavior of this circuit.<br> (en)
  • Polymorfní hradla jsou schopna vykonávat jednu nebo více přidružených logických funkcí k hlavní funkci obvodu. Tyto přidružené funkce mohou být aktivovány za jistých okolností změnou řídicích parametrů obvodu (jako jsou např. teplota, Vdd, světlo apod.). Článek představuje netriviální polymorfní obvod, který byl navržen na úrovni hradel a potom simulován na úrovni tranzitorů s využitím polymorfního hradla NAND/NOR řízeného Vdd a běžných hradel.&nbsp; (cs)
Title
  • Novel Logic Circuits Controlled by Vdd
  • Novel Logic Circuits Controlled by Vdd (en)
  • Nové logické obvody řizené napájecím napětím (cs)
skos:prefLabel
  • Novel Logic Circuits Controlled by Vdd
  • Novel Logic Circuits Controlled by Vdd (en)
  • Nové logické obvody řizené napájecím napětím (cs)
skos:notation
  • RIV/00216305:26230/06:PU66942!RIV07-GA0-26230___
http://linked.open.../vavai/riv/strany
  • 85-86
http://linked.open...avai/riv/aktivita
http://linked.open...avai/riv/aktivity
  • P(GA102/06/0599)
http://linked.open...vai/riv/dodaniDat
http://linked.open...aciTvurceVysledku
http://linked.open.../riv/druhVysledku
http://linked.open...iv/duvernostUdaju
http://linked.open...titaPredkladatele
http://linked.open...dnocenehoVysledku
  • 489166
http://linked.open...ai/riv/idVysledku
  • RIV/00216305:26230/06:PU66942
http://linked.open...riv/jazykVysledku
http://linked.open.../riv/klicovaSlova
  • polymorphic gate, logic circuit, evolutionary design (en)
http://linked.open.../riv/klicoveSlovo
http://linked.open...ontrolniKodProRIV
  • [9699B9B5F56C]
http://linked.open...v/mistoKonaniAkce
  • Praha
http://linked.open...i/riv/mistoVydani
  • Praha
http://linked.open...i/riv/nazevZdroje
  • Proc. of 2006 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop
http://linked.open...in/vavai/riv/obor
http://linked.open...ichTvurcuVysledku
http://linked.open...cetTvurcuVysledku
http://linked.open...vavai/riv/projekt
http://linked.open...UplatneniVysledku
http://linked.open...iv/tvurceVysledku
  • Kotásek, Zdeněk
  • Sekanina, Lukáš
  • Stareček, Lukáš
http://linked.open...vavai/riv/typAkce
http://linked.open.../riv/zahajeniAkce
number of pages
http://purl.org/ne...btex#hasPublisher
  • IEEE Computer Society
https://schema.org/isbn
  • 1-4244-0184-4
http://localhost/t...ganizacniJednotka
  • 26230
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