About: High-Level Modelling, Analysis, and Verification on FPGA-Based Hardware Design

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rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	The paper presents high-level modelling and formal analysis and verification on an FPGA-based multigigabit network monitoring system called Scampi. Uppaal was applied in this work to establish some correctness and throughput results on a model intentionally built using patterns reusable in other similar projects. Some initial experiments with parametric analysis using TReX were performed too. The paper presents high-level modelling and formal analysis and verification on an FPGA-based multigigabit network monitoring system called Scampi. Uppaal was applied in this work to establish some correctness and throughput results on a model intentionally built using patterns reusable in other similar projects. Some initial experiments with parametric analysis using TReX were performed too. (en)
Title	High-Level Modelling, Analysis, and Verification on FPGA-Based Hardware Design High-Level Modelling, Analysis, and Verification on FPGA-Based Hardware Design (en)
skos:prefLabel	High-Level Modelling, Analysis, and Verification on FPGA-Based Hardware Design High-Level Modelling, Analysis, and Verification on FPGA-Based Hardware Design (en)
skos:notation	RIV/00216305:26230/05:PU56455!RIV10-MSM-26230___
http://linked.open...avai/riv/aktivita	P Z
http://linked.open...avai/riv/aktivity	P(GA102/04/0780), P(GA102/05/0723), Z(MSM6383917201)
http://linked.open...vai/riv/dodaniDat	2010
http://linked.open...aciTvurceVysledku	Vojnar, Tomáš Matoušek, Petr Smrčka, Aleš
http://linked.open.../riv/druhVysledku	D - Článek ve sborníku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	Vysoké učení technické v Brně / Fakulta informačních technologií
http://linked.open...dnocenehoVysledku	523308
http://linked.open...ai/riv/idVysledku	RIV/00216305:26230/05:PU56455
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	formal analysis and verification, timed automata, parametric analysis, FPGA, hardware, computer networks<br> (en)
http://linked.open.../riv/klicoveSlovo	parametric analysis formal analysis and verification FPGA timed automata hardware computer networks<br>
http://linked.open...ontrolniKodProRIV	[427F43B23673]
http://linked.open...v/mistoKonaniAkce	Saarbruecken
http://linked.open...i/riv/mistoVydani	Berlin
http://linked.open...i/riv/nazevZdroje	Correct Hardware Design and Verification Methods
http://linked.open...in/vavai/riv/obor	JC
http://linked.open...ichTvurcuVysledku	3 (xsd:int)
http://linked.open...cetTvurcuVysledku	3 (xsd:int)
http://linked.open...vavai/riv/projekt	Automated methods and tools supporting development of reliable concurrent and distributed systems A Framework for Formal Specifications and Prototyping of Information System's Network Applications
http://linked.open...UplatneniVysledku	2005
http://linked.open...iv/tvurceVysledku	Vojnar, Tomáš Matoušek, Petr Smrčka, Aleš
http://linked.open...vavai/riv/typAkce	WRD - Světová
http://linked.open.../riv/zahajeniAkce	2005-10-03 (xsd:date)
http://linked.open...n/vavai/riv/zamer	Optical National Research Network and Its New Applications
number of pages	5 (xsd:int)
http://purl.org/ne...btex#hasPublisher	Springer-Verlag
https://schema.org/isbn	978-3-540-29105-3
http://localhost/t...ganizacniJednotka	26230
is http://linked.open...avai/riv/vysledek of	High-Level Modelling, Analysis, and Verification on FPGA-Based Hardware Design

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