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Description
  • Příspěvek se zabývá problémem výběru vhodné množiny registrů do řetězce scan. Proces výběru prezentovaný v příspěvku je založen na technikách identifikace testovatelných jader, pokrytí zpětnovazebních smyček a výběru vhodných registrů pro dosažení vysokého paralelismu testu. (cs)
  • In the paper, the solution of the problem of selecting the most optimal design-for-testability technique for register-transfer level digital circuits is demonstrated. A decision-making process that is able to solve the problem over a set of scan-based techniques is presented in the paper. The process decides among following testability improving techniques: identification of testable cores, covering of feedback loops by minimum set of scan registers, selection of registers into scan chains to achieve hiigh level of parallelism during the test application.
  • In the paper, the solution of the problem of selecting the most optimal design-for-testability technique for register-transfer level digital circuits is demonstrated. A decision-making process that is able to solve the problem over a set of scan-based techniques is presented in the paper. The process decides among following testability improving techniques: identification of testable cores, covering of feedback loops by minimum set of scan registers, selection of registers into scan chains to achieve hiigh level of parallelism during the test application. (en)
Title
  • Methodology of Selecting Scan-Based Testability Improving Technique
  • Methodology of Selecting Scan-Based Testability Improving Technique (en)
  • Methodology of Selecting Scan-Based Testability Improving Technique (cs)
skos:prefLabel
  • Methodology of Selecting Scan-Based Testability Improving Technique
  • Methodology of Selecting Scan-Based Testability Improving Technique (en)
  • Methodology of Selecting Scan-Based Testability Improving Technique (cs)
skos:notation
  • RIV/00216305:26230/05:PU55724!RIV06-GA0-26230___
http://linked.open.../vavai/riv/strany
  • 186-189
http://linked.open...avai/riv/aktivita
http://linked.open...avai/riv/aktivity
  • P(GA102/04/0737)
http://linked.open...vai/riv/dodaniDat
http://linked.open...aciTvurceVysledku
http://linked.open.../riv/druhVysledku
http://linked.open...iv/duvernostUdaju
http://linked.open...titaPredkladatele
http://linked.open...dnocenehoVysledku
  • 529739
http://linked.open...ai/riv/idVysledku
  • RIV/00216305:26230/05:PU55724
http://linked.open...riv/jazykVysledku
http://linked.open.../riv/klicovaSlova
  • design for testability, scan method, testable core (en)
http://linked.open.../riv/klicoveSlovo
http://linked.open...ontrolniKodProRIV
  • [EAAD2BD929A1]
http://linked.open...v/mistoKonaniAkce
  • Sopron
http://linked.open...i/riv/mistoVydani
  • Sopron
http://linked.open...i/riv/nazevZdroje
  • Proc. of 8th IEEE Design and Diagnostic of Electronic Circuits and Systems Workshop
http://linked.open...in/vavai/riv/obor
http://linked.open...ichTvurcuVysledku
http://linked.open...cetTvurcuVysledku
http://linked.open...vavai/riv/projekt
http://linked.open...UplatneniVysledku
http://linked.open...iv/tvurceVysledku
  • Kotásek, Zdeněk
  • Strnadel, Josef
  • Pečenka, Tomáš
http://linked.open...vavai/riv/typAkce
http://linked.open.../riv/zahajeniAkce
number of pages
http://purl.org/ne...btex#hasPublisher
  • University of West Hungary
https://schema.org/isbn
  • 963-9364-48-7
http://localhost/t...ganizacniJednotka
  • 26230
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