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Description
| - The work deals with testability analysis of data-path within register-transfer level digital circuits and with utilizing its results in selected areas in digital circuit diagnostics area. In the work, it is shown that it is advantageous if each module stored in a design library is equipped both with design-related information and special diagnostics-related information usable for testability-analysis purposes in our case. During our research, such information was described by means of a formal mathematiical model based on so-called transparency conception. Proposed digraph-search based testability analysis method is described by means of instruments specified in the model.
- The work deals with testability analysis of data-path within register-transfer level digital circuits and with utilizing its results in selected areas in digital circuit diagnostics area. In the work, it is shown that it is advantageous if each module stored in a design library is equipped both with design-related information and special diagnostics-related information usable for testability-analysis purposes in our case. During our research, such information was described by means of a formal mathematiical model based on so-called transparency conception. Proposed digraph-search based testability analysis method is described by means of instruments specified in the model. (en)
- Článek se zabývá analýzou datové cesty číslicového obvodu na úrovni meziregistrových přenosů a využitím jejích výsledků ve vybraných oblastech diagnostiky číslicových systémů. Metoda je založena na tzv. virtuálních portech, konstrukci dvojice speciálníchorientovaných grafů (graf datového toku testovacích vzorků, graf datového toku odezev) a jejich analýze. (cs)
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Title
| - VIRTA: Virtual Port Based Register-Transfer Level Testability Analysis and Improvements
- VIRTA: Analýza a zlepšení testovatelnosti založená na virtuálních portech (cs)
- VIRTA: Virtual Port Based Register-Transfer Level Testability Analysis and Improvements (en)
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skos:prefLabel
| - VIRTA: Virtual Port Based Register-Transfer Level Testability Analysis and Improvements
- VIRTA: Analýza a zlepšení testovatelnosti založená na virtuálních portech (cs)
- VIRTA: Virtual Port Based Register-Transfer Level Testability Analysis and Improvements (en)
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skos:notation
| - RIV/00216305:26230/05:PU55722!RIV06-GA0-26230___
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http://linked.open.../vavai/riv/strany
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http://linked.open...avai/riv/aktivita
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http://linked.open...avai/riv/aktivity
| - P(GA102/04/0737), P(GP102/05/P193)
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http://linked.open...vai/riv/dodaniDat
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http://linked.open...aciTvurceVysledku
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http://linked.open.../riv/druhVysledku
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http://linked.open...iv/duvernostUdaju
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http://linked.open...titaPredkladatele
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http://linked.open...dnocenehoVysledku
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http://linked.open...ai/riv/idVysledku
| - RIV/00216305:26230/05:PU55722
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http://linked.open...riv/jazykVysledku
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http://linked.open.../riv/klicovaSlova
| - Testability analysis, data-path, register-transfer level, transparency, I-path concept, virtual port, digraph, test-pattern data-flow digraph, test-response data-flow digraph, graph algorithm, design for testability, scan, benchmark circuit. (en)
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http://linked.open.../riv/klicoveSlovo
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http://linked.open...ontrolniKodProRIV
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http://linked.open...v/mistoKonaniAkce
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http://linked.open...i/riv/mistoVydani
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http://linked.open...i/riv/nazevZdroje
| - Proceedings of 8th IEEE Design and Diagnostic of Electronic Circuits and Systems Workshop
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http://linked.open...in/vavai/riv/obor
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http://linked.open...ichTvurcuVysledku
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http://linked.open...cetTvurcuVysledku
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http://linked.open...vavai/riv/projekt
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http://linked.open...UplatneniVysledku
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http://linked.open...iv/tvurceVysledku
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http://linked.open...vavai/riv/typAkce
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http://linked.open.../riv/zahajeniAkce
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number of pages
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http://purl.org/ne...btex#hasPublisher
| - University of West Hungary
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https://schema.org/isbn
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http://localhost/t...ganizacniJednotka
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is http://linked.open...avai/riv/vysledek
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