About: VIRTA: Virtual Port Based Register-Transfer Level Testability Analysis and Improvements

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rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	The work deals with testability analysis of data-path within register-transfer level digital circuits and with utilizing its results in selected areas in digital circuit diagnostics area. In the work, it is shown that it is advantageous if each module stored in a design library is equipped both with design-related information and special diagnostics-related information usable for testability-analysis purposes in our case. During our research, such information was described by means of a formal mathematiical model based on so-called transparency conception. Proposed digraph-search based testability analysis method is described by means of instruments specified in the model. The work deals with testability analysis of data-path within register-transfer level digital circuits and with utilizing its results in selected areas in digital circuit diagnostics area. In the work, it is shown that it is advantageous if each module stored in a design library is equipped both with design-related information and special diagnostics-related information usable for testability-analysis purposes in our case. During our research, such information was described by means of a formal mathematiical model based on so-called transparency conception. Proposed digraph-search based testability analysis method is described by means of instruments specified in the model. (en) Článek se zabývá analýzou datové cesty číslicového obvodu na úrovni meziregistrových přenosů a využitím jejích výsledků ve vybraných oblastech diagnostiky číslicových systémů. Metoda je založena na tzv. virtuálních portech, konstrukci dvojice speciálníchorientovaných grafů (graf datového toku testovacích vzorků, graf datového toku odezev) a jejich analýze. (cs)
Title	VIRTA: Virtual Port Based Register-Transfer Level Testability Analysis and Improvements VIRTA: Analýza a zlepšení testovatelnosti založená na virtuálních portech (cs) VIRTA: Virtual Port Based Register-Transfer Level Testability Analysis and Improvements (en)
skos:prefLabel	VIRTA: Virtual Port Based Register-Transfer Level Testability Analysis and Improvements VIRTA: Analýza a zlepšení testovatelnosti založená na virtuálních portech (cs) VIRTA: Virtual Port Based Register-Transfer Level Testability Analysis and Improvements (en)
skos:notation	RIV/00216305:26230/05:PU55722!RIV06-GA0-26230___
http://linked.open.../vavai/riv/strany	190-193
http://linked.open...avai/riv/aktivita	P
http://linked.open...avai/riv/aktivity	P(GA102/04/0737), P(GP102/05/P193)
http://linked.open...vai/riv/dodaniDat	2006
http://linked.open...aciTvurceVysledku	Strnadel, Josef
http://linked.open.../riv/druhVysledku	D - Článek ve sborníku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	Vysoké učení technické v Brně / Fakulta informačních technologií
http://linked.open...dnocenehoVysledku	548869
http://linked.open...ai/riv/idVysledku	RIV/00216305:26230/05:PU55722
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	Testability analysis, data-path, register-transfer level, transparency, I-path concept, virtual port, digraph, test-pattern data-flow digraph, test-response data-flow digraph, graph algorithm, design for testability, scan, benchmark circuit. (en)
http://linked.open.../riv/klicoveSlovo	I-path concept Testability analysis benchmark circuit. data-path test-pattern data-flow digraph test-response data-flow digraph digraph transparency scan virtual port design for testability register-transfer level graph algorithm
http://linked.open...ontrolniKodProRIV	[00B965877FB7]
http://linked.open...v/mistoKonaniAkce	Sopron
http://linked.open...i/riv/mistoVydani	Sopron
http://linked.open...i/riv/nazevZdroje	Proceedings of 8th IEEE Design and Diagnostic of Electronic Circuits and Systems Workshop
http://linked.open...in/vavai/riv/obor	JC
http://linked.open...ichTvurcuVysledku	1 (xsd:int)
http://linked.open...cetTvurcuVysledku	1 (xsd:int)
http://linked.open...vavai/riv/projekt	Modern methods of digital system synthesis Optimizing Methods in Digital Systems Diagnosis
http://linked.open...UplatneniVysledku	2005
http://linked.open...iv/tvurceVysledku	Strnadel, Josef
http://linked.open...vavai/riv/typAkce	WRD - Světová
http://linked.open.../riv/zahajeniAkce	2005-04-13 (xsd:date)
number of pages	4 (xsd:int)
http://purl.org/ne...btex#hasPublisher	University of West Hungary
https://schema.org/isbn	963-9364-48-7
http://localhost/t...ganizacniJednotka	26230
is http://linked.open...avai/riv/vysledek of	VIRTA: Virtual Port Based Register-Transfer Level Testability Analysis and Improvements

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